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A Domain Specific On-Chip Network Design for Large Scale Cache Systems

In the quest for high-performance computing, large caches in systems often lead to increased access times and underutilization of network resources. This paper introduces a single-stage multicast router and a new network topology designed for large caches, employing innovative routing algorithms and a Fast-LRU replacement policy. The objective is to minimize network overhead while maintaining performance standards. By optimizing link usage and reducing buffer needs, the proposed architecture aims to enhance overall efficiency and reduce power consumption in large-scale cache systems.

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A Domain Specific On-Chip Network Design for Large Scale Cache Systems

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  1. A Domain Specific On-Chip Network Design for Large Scale Cache Systems Yuho Jin, Eun Jung Kim, Ki Hwan Yum HPCA 2007

  2. Motivation • Large caches are becoming the norm of the day • Not optimized/ larger access times • Overprovision and underutilization of network resources(!!) • Can same performance be achieved with lesser resources?

  3. Contributions • Single stage multicast router • Not really new! (Not really feasible??) • New network topology for large caches (banks) • Minimizes the number of links in system • A new routing algorithm • For the new topology • A new replacement policy in NUCA caches • FAST-LRU, exploits multicast Overall aim was to reduce network overhead for minimal performance loss!!

  4. Router Architecture • 4 VCs per PC • Near 1 stage router • Look-ahead routing • Buffer bypass • Spec Switch Alloc • Arbitration precomputation Co-ordinate System

  5. Multicast Support • Multicast: Sync vs Async • Async Multicast => flit replication=> buffer space • Do it without extra h/w? • Use existing VC buffers • Copy flit to a different PC buffer • Use lesser used PCs • Get a free VC • Send flit to different destinations Figure courtesy: Chita R Das, OCIN ‘06

  6. Set Associative Cache

  7. Fast-LRU Replacement • Bank Set arrangement - Sets distributed among banks Column ..……… S0, W1 ……… S1, W0 S0, W2 ……… S0, W3 ……… S0, W4 ………

  8. Multicast Fast-LRU

  9. Network Topology Access Patterns • A – data request • B: Check for data • B/C: Move data • D/E : Data to Core • A’/B’: Hit or Miss • F: Data delivery from mem to MRU • G: Dirty block to mem

  10. Network Topology => Horizontal Links mostly not required Except here!!

  11. The HALO Network

  12. Implications • Underutilized links removed => simplified network, area savings(?) • Power savings come for free!! (lesser buffers) • Links removed => constrained routing • XYX routing proposed • XY is dimension order • Algorithm simplified - • If going from core/mem to $ bank travel horizontal first • If going from $ bank to core/mem, travel vertical first

  13. Example Yoff = -ve , Xoff = +ve -> Channel = Y-

  14. Example Yoff = +ve, Xoff = +ve Channel -> X+, then Y+

  15. Results

  16. Results Avg Access latency They target to optimize network latency – 50 -60% of total latency

  17. IPC Comparisons

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