1 / 6

ITRS Roadmap for Lower Power Design

Understand the ITRS roadmap for lower power design, including scaling factors, interconnect power reduction methods, and clock gating. Learn how gate, drain, source scaling impacts capacitance, voltage, and frequency.

barrymaddox
Télécharger la présentation

ITRS Roadmap for Lower Power Design

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. CSE 252A Integrated Circuit Layout Automation Lecture 2: ITRS Roadmap and Lower Power Design Methodology Winter 2009 Chung-Kuan Cheng

  2. Agenda • Scaling • ITRS Roadmap

  3. Scaling -- Gate Drain Scaling Factor is S Drain Gate Source Source

  4. Scaling -- Gate • Capacitance is proportional to S • Voltage is proportional to S • Frequency is inverse proportional to S

  5. Scaling – Transmission Line W W

  6. Interconnect • Ways to reduce interconnect power consumption • Shorter wire length • More spacing • Clock gating

More Related