1. Resetting FSMs

2. Reset must be asserted 0 V Reset Requirements • If VCC is less than a part’s guaranteed operating range, then it must be held in reset. VCC Nominal, e.g., 5.0V VCC min, e.g., 4.5V

3. Time for synchronously reset circuits to reset VCC ramps to oscillator min VCC Oscillator max start-up time Release reset Turn on Reset Requirements • If a clocked part’s clock is not running, then it must be held in reset

4. CLK CMD RESET CMD Execution circuit SC_SELF_DESTRUCT CMD_ENA From previously turned-on module Reset Requirements • No part should be allowed to issue critical commands until it is fully functional

5. Reset Requirements • Many parts have internal power-on reset detectors: • FPGAs • PROMs • PALs • Understand EXACTLY what each part does when powering up and down. • Hint: it may not match the data sheet. • Ensure that the release of the PORs and activities are well coordinated.

6. Reset Requirements • Be aware of the turn-on behavior of the parts in the system, and design the reset and command execution circuits appropriately. • Example 1: Does your reset require the clock to be ticking?

7. A Flight Oscillator Start Time 200 kHz +5V 10 ms/div; tRISE = 50 ms

8. A Flight Oscillator Start Time Summary

9. Synchronous Reset • FPGA may not be functional during power-on transient • Crystal oscillator start time

10. Start up TransientCharge Pump and Isolation Antifuses CHARGE PUMP Takes time to start and turn on FETs

11. But What About Asynchronous Clear, Synchronous Removal? • For many devices, applying the reset asynchronously does not help • Charge pump not started; reset can’t get in, signal can’t get out. • I/Os out of control • Logic not yet loaded into part • Increases vulnerability to noise

12. Start up Transient - Outputs Fire Cover Arm VCC Hor: 5 ms/Division; Ver: 2 volts/Div This transient led to the loss of a spacecraft mission.

13. Act 3 Performance vs. Spec • The Specification • Normal operation for inputs and outputs will occur within 100 µs after VCC reaches 2.75 V. Before reaching the point of normal operation, all inputs and outputs are in a high impedance state (tristate) regardless of VCC rise time. ICC rises to 10-60 mA when VCC is between 2V and 3V and then returns to normal. • "A Power-On Reset (POR) Circuit for Actel Devices," FPGA Data Book and Design Guide, Actel Corp., 1995, pp. 3-81 to 3-82.

14. Act 3 Performance vs. Spec This was one example and one case; the output was not in tri-state. Note that there was a "memory effect" and that the results were not fully repeatable; there were some random variations. For the newer SX-S devices, with “safe start,” lab results indicated that the startup is not safe, depends on the power-up sequence, … Design conservatively.

15. Reset Requirements • On power-down, requirements 1-4 must be observed: • Reset must be asserted before VCC falls to below VCC min and be asserted until VCC = 0 • Reset must be asserted early enough to allow sequential parts to reset • Critical commands must be suppressed • Be aware of power-down behavior of parts

16. VCC nominal, e.g., 5.0V Be sure reset is not asserted here Power supply VCC min Be sure reset is asserted here 0 V Practical Considerations • Be aware of power supply tolerance Part VCCc min, e.g., 4.5V

17. Practical Considerations • The best PORs come from the power supply • Can be powered from a separate circuit that comes up before the main converter, e.g., the bootstrap converter • Can be asserted before the main supply is powered up • Was done on Galileo