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A detailed analysis of stages, input latches, and intersection pipelines of a ray-BVH system for real-time rendering. The pipeline architecture includes extent testing, intersection checks, and hit detection for efficient rendering.
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Stage 1 Ray Extent Test clk hit clock Input Latches Stage 2 clk Ray-BVH Intersect hit Top Level Ray-BVH Intersection Pipeline
rexmin reymin rezmin 2:1 2:1 2:1 2:1 2:1 MagCmp MagCmp MagCmp MagCmp MagCmp xmin ymin zmin xmax ymax zmax rexmax reymax rezmax rez ry rx rz rex rey rxs rys rzs rxs’ rys’ rzs’ 2:1 MagCmp < > < > < > > < > < > < rxs b:2:1 b:2:1 b:2:1 b:2:1 b:2:1 b:2:1 rys rzs ray.t HIT Stage 1: Ray Extent Test
rx ry rz rx ry rz xmin ymin zmin xmax ymax zmax - - - - - - xa ya za xb yb zb ri rj rxs rys Ebnd rk ri rxs rzs Ebnd rj rk rys rzs Ebnd ri:rj case rk:ri case rj:rk case HIT HIT HIT HIT Stage 2: Ray-BVH Intersect
ya yb xb xa xa xb yb ya M1 P1 M2 P2 M2 P2 M1 P1 ri 2:1 rj 2:1 rj 2:1 ri 2:1 * * * * Ebnd Ebnd - - MagCmp MagCmp < < HIT Stage 2: ri:rj case
xa xb zb za za zb xb xa M3 P3 M1 P1 M1 P1 M3 P3 rk 2:1 ri 2:1 ri 2:1 rk 2:1 * * * * Ebnd Ebnd - - MagCmp MagCmp < < HIT Stage 2: rk:ri case
za zb yb ya ya yb zb za M2 P2 M3 P3 M3 P3 M2 P2 rj 2:1 rk 2:1 rk 2:1 rj 2:1 * * * * Ebnd Ebnd - - MagCmp MagCmp < < HIT Stage 2: rj:rk case
random drawing components HIT M1
