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LECTURE 6: State machines

EECS 318 CAD Computer Aided Design. LECTURE 6: State machines. Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow. VHDL Component, Entity, and Architecture . for-generate | if generate.

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LECTURE 6: State machines

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  1. EECS 318 CADComputer Aided Design LECTURE 6: State machines Instructor: Francis G. Wolff wolff@eecs.cwru.edu Case Western Reserve University This presentation uses powerpoint animation: please viewshow CWRU EECS 318

  2. VHDL Component,Entity, and Architecture for-generate | if generate Component Instance Component Declaration Entity Architecturei ConcurrentWith-Select-WhenWhen-Else ConcurrentBoolean Equations OtherConcurrentComponents CWRU EECS 318

  3. VHDL Components Add ; only if another identifier Component Declaration [ Optional ] { repeat } COMPONENT component_entity_name[ GENERIC ( {identifier: type [:= initial_value ];} ) ][ PORT ( { identifier: mode type; }) ]END; Component Instance identifier : component_entity_name[ GENERIC MAP ( identifier { ,identifier} ) ][ PORT MAP ( identifier { ,identifier})]; mode := IN | OUT | INOUT type := std_logic | std_logic_vector(n downto 0) | bit CWRU EECS 318

  4. VHDL Concurrent Statements Boolean Equations relation::=relationLOGICrelation|NOT relation | ( relation ) LOGIC::= AND | OR | XOR | NAND | NOR | XNOR Multiplexor case statement WITH select_signal SELECTsignal <= signal_value1 WHEN select_compare1,• • •WHEN select_comparen; Example: y <= NOT ( NOT (a) AND NOT (b) ) Example: 2 to 1 multiplexorWITH s SELECT y <= a WHEN ‘0’, b WHEN OTHERS; CWRU EECS 318

  5. VHDL Concurrent Statements Conditionial signal assignment signal <= signal_value1 WHEN condition1 ELSE• • •signal_valuen WHEN conditionn; ELSEsignal_valuen+1 Example: Priority Encoder y <= a WHEN s=‘0’ ELSE b; CWRU EECS 318

  6. SR Flip-Flop (Latch) NANDRSQn+10 0 U0 1 11 0 01 1 Qn NORRSQn+10 0 Qn0 1 11 0 01 1 U R Q Q S R Q Q S Q <= R NOR NQ;NQ <= S NOR Q; Q <= R NAND NQ;NQ <= S NAND Q; CWRU EECS 318

  7. SR Flip-Flop (Latch) R(t) NANDRSQn+10 0 U0 1 11 0 01 1 Qn 5ns Q(t + 5ns) Q(t) Q(t) Q(t + 5ns) 5ns S(t) With Delay R Q t 0 5ns 10ns 15ns 20ns 25ns 30ns 35ns 40ns R 1 1 0 0 0 0 1 1 1Q U U U U 0 0 0 0 0 Q U U U 1 1 1 1 1 1S 1 1 1 1 1 1 1 1 1 Q S Example: R <= ‘1’, ‘0’ after 10ns, ‘1’ after 30ns; S <= ‘1’; CWRU EECS 318

  8. Gated-Clock SR Flip-Flop (Latch Enable) PS CLR Q <= (S NAND LE) NAND NQ; S NQ <= (R NAND LE) NAND Q; Q LE Synchronous: Set and Reset Q R Asynchronous: Preset and Clear Latches require that during the gated-clock the data must also be stable (i.e. S and R) at the same time Suppose each gate was 5ns: how long does the clock have to be enabled to latch the data? Answer: 15ns CWRU EECS 318

  9. Rising-Edge Flip-flop CWRU EECS 318

  10. Rising-Edge Flip-flop logic diagram CWRU EECS 318

  11. Synchronous Sequential Circuit CWRU EECS 318

  12. Abstraction: Finite State Machine CWRU EECS 318

  13. FSM Representations CWRU EECS 318

  14. Simple Design Example CWRU EECS 318

  15. State Encoding CWRU EECS 318

  16. Logic Implementations CWRU EECS 318

  17. FSM Observations CWRU EECS 318

  18. Coke Machine Example CWRU EECS 318

  19. Coke Machine State Diagram CWRU EECS 318

  20. Coke Machine Diagram II CWRU EECS 318

  21. Moore Machines CWRU EECS 318

  22. Mealy Machines CWRU EECS 318

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