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SEMI 3DS-IC Standards Activities (Three-dimensional Stacked Integrated Circuits)

SEMI 3DS-IC Standards Activities (Three-dimensional Stacked Integrated Circuits). Liaison Report September 2012. 3DS-IC Standards Committee Charter. To explore, evaluate, discuss, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will;

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SEMI 3DS-IC Standards Activities (Three-dimensional Stacked Integrated Circuits)

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  1. SEMI 3DS-IC Standards Activities(Three-dimensional Stacked Integrated Circuits) Liaison Report September 2012 SEMI 3DS-IC Standards Activities - September 2012

  2. 3DS-IC Standards CommitteeCharter • To explore, evaluate, discuss, and create consensus-based specifications, guidelines, and practices that, through voluntary compliance, will; • promote mutual understanding and improved communication between users and suppliers of 3DS-IC materials, carriers, automation systems and devices, and • enhance the manufacturing efficiency and capability and shorten time-to-market so as to reduce manufacturing cost in the 3DS-IC industry. • Committee formed in Fall 2010 • Inaugural meeting held in January 12, 2011 SEMI 3DS-IC Standards Activities - September 2012

  3. Participating Companies*Over 140 registered TC members *partial list SEMI 3DS-IC Standards Activities - September 2012

  4. Leadership • Committee Co-chairs • Urmi Ray (Qualcomm) • Sesh Ramaswami (Applied Materials) • Chris Moore (Semilab) • Rich Allen (SEMATECH) SEMI 3DS-IC Standards Activities - September 2012

  5. Organization Chart • NA 3DS-IC Committee • Chairs: • Urmi Ray (Qualcomm) • Sesh Ramaswami (Applied Materials) • Chris Moore (Semilab) • Rich Allen (SEMATECH) • Wafer Bonded StacksTask Force • Leader: • Rich Allen (SEMATECH) • Thin Wafer HandlingTask Force • Leader: • Urmi Ray (Qualcomm) • Raghunandan Chaware (Xilinx) • Richard Allen (SEMATECH) • Inspection & MetrologyTask Force • Leader: • Yi-Shao Lai (ASE) • David Read (NIST) • Chris Moore (Semilab) • Victor Vartanian (SEMATECH) SEMI 3DS-IC Standards Activities - September 2012

  6. Task Force Overview • 3DS-IC Wafer Bonded Stacks TF • Approved late January 2011 • Charter: • The BWS Task Force will actively create and/or modify specifications that reflect bonded wafer stacks parameters and the wafer bonding process. • Scope: • Identify new wafer parameters that reflect adequate ranges for bonded wafer stacks • Modify/create document to reflect adequate ranges for bonded wafer stacks • Identify other SEMI standards that are adversely affected by BWS parameters • Update referenced standards: create/modify standards to reflect BWS parameters SEMI 3DS-IC Standards Activities - September 2012

  7. Task Force Overview • 3DS-IC Inspection & Metrology TF • Approved late January 2011 • Charter: • Develop standards for metrology and inspection methods to be used in measuring the properties of TSV’s, bonded wafer stacks, and dies used in the 3DS-IC manufacturing process. • Scope: • Examples of needed standards include (but are not limited to): • TSV physical properties (i.e., depth, top, bottom CD, side wall, etc.) • Bonded wafer stack properties (i.e., overlay, bond inspection) • Defect metrology • Dies SEMI 3DS-IC Standards Activities - September 2012

  8. Task Force Overview • 3DS-IC Thin Wafer Handling TF • Approved late January 2011 • Charter: • Develop standards for reliable handling and shipping of thin wafers, dies (e.g., Micro-pillar Grid array -MPGA) used in 3DS-IC high-volume manufacturing (HVM) • Define thin wafer handling requirements including physical interfaces used in 3DS-IC manufacturing • Define shipping requirements, including packaging, reliability, and other relevant criteria. This will also include MPGA ship/handle requirements SEMI 3DS-IC Standards Activities - September 2012

  9. Task Force Overview • 3DS-IC Thin Wafer Handling TF (cont’d) • Scope: • Formulate a common set of requirements and prioritize critical areas for standardization, resulting in a short-list of required standards (inspection, shipping etc) in the topics listed below. Other topics may be added based on additional inputs • Thin wafer and Die Shipping related activities: • Examples: Shipping carriers for thin wafer (wafer cassette, box or frame), Shipping carrier for dies (MPGA), Reliability Test methods • Transportation vibration testing • Drop-shock • Other – new tests? • Thin wafer handling-related activities: • Examples: Process and Metrology Tools and Test methods • Whole wafer inspection for damage (crack, break etc)Macro level • Damage to features – microbump, pad etc micro level • Universal carrier concept • Automation SEMI 3DS-IC Standards Activities - September 2012

  10. Meeting InformationNA 3DS-IC Committee • Last meeting • July 10 for SEMICON West 2012San Francisco, California • Next meeting • October 30 for NA Fall 2012 MeetingsSan Jose, California SEMI 3DS-IC Standards Activities - September 2012

  11. Document Review Summary SEMI 3DS-IC Standards Activities - September 2012

  12. SNARFs [1/2](Standards New Activity Report Form) SEMI 3DS-IC Standards Activities - September 2012

  13. SNARFs [2/2](Standards New Activity Report Form) SEMI 3DS-IC Standards Activities - September 2012

  14. NA 3DS-IC Ballots www.semi.org/standardsballots • Bonded Wafer Stacks TF • Draft Document 5173A was adjudicated at SEMICON West and was sent back to the task force rework • New Standard: Guide for Describing Materials Properties and Test Methods for a 300 mm 3DS-IC Wafer Stack • Document 5173B will be reballoted for the Cycle 6, 2012 voting period • Inspection & Metrology TF • Draft Document 5269A passed technical committee review (with editorial changes) at SEMICON West 2012 • New Standard: Guide for Terminology for Measured Geometrical Parameters of Through-Silicon Vias (TSVs) in 3DS-IC Structures • Document 5269A passed both technical committee and procedural reviews. To be published as SEMI 3D1 SEMI 3DS-IC Standards Activities - September 2012

  15. NA 3DS-IC Fall 2012 Meeting Schedule • North America Standards Fall 2012 Meetings • October 29 to November 1 • SEMI Headquarters3081 Zanker RoadSan Jose, California / U.S.A. • Tuesday, October 30 • Inspection & Metrology TF (8:00 AM to 10:00 AM) • Bonded Wafer Stacks TF (10:00 AM to 12:00 Noon) • Thin Wafer Handling TF (1:00 PM to 3:00 PM) • NA 3DS-IC Committee (3:00 PM to 5:00 PM) SEMI 3DS-IC Standards Activities - September 2012

  16. NARSC NA Standards Fall 2012 MeetingsOctober 29 – November 1 3DS-IC EH&S Facilities & Gases HB-LED Information & Control Liquid Chemicals Scheduleat-a-glance MEMS/NEMS Metrics PV / PV Materials Physical Interfaces & Carriers Silicon Wafer Traceability SEMI 3DS-IC Standards Activities - September 2012

  17. Thank you! • For more information, please visit the SEMI 3DS-IC Google Site: • https://sites.google.com/a/semi.org/3dsic/ • For more information or to participate in any NA 3DS-IC activities, please contact: • Paul TrioSEMI North America Standardsptrio@semi.org SEMI 3DS-IC Standards Activities - September 2012

  18. Taiwan 3DS-IC Committee Overview SEMI 3DS-IC Standards Activities - September 2012

  19. Organization Chart • Taiwan 3DS-IC Committee • Chairs: • Tzu-Kun Ku (ITRI) • Wendy Chen (King Yuan Electronics) • Yi-Shao Lai (ASE) NEW! • TestingTask Force • Leader: • Sam Ko (KYEC) • Roger Hwang (ASE) • Tzong-Tsong Miau (ITRI) • Middle End ProcessTask Force • Leader: • Arthur Chen (NTUST) • Erh Hao Chen (ITRI) • Jerry Yang (SEMATECH) TW 3DS-IC formed: Jul 2011 SEMI 3DS-IC Standards Activities - September 2012

  20. Meeting Information • Last meeting • June 6, 2012Hsinchu, Taiwan • Next meeting • September 6 for SEMICON Taiwan 2012Taipei, Taiwan SEMI 3DS-IC Standards Activities - September 2012

  21. Task Force Overview • Taiwan 3DS-IC Test Task Force • Formed on October 26, 2011 • Charter: • The Testing Task Force will develop standards, guidelines, and/or specifications for electrical testing related activities used in 3DS-IC manufacturing for the ultimate goal of yield enhancement. • Scope: • Activities related to electrical testing of prebond and bonded wafers/devices include (but not limited to): • Design for Test (DfT) such as test structures and placement; • Test methodologies such as contact method and test procedures; • Test fixtures such as probe card and probe interfaces, and • Data mining test results. SEMI 3DS-IC Standards Activities - September 2012

  22. Task Force Overview • New! Middle-End Process Task Force • Formed on February 9, 2012 • Charter: • Develop the standards and define the specifications for middle-end process (MEOL) related manufacturing flow. Current Phase of Standard and Specification development focused on the middle-end process on wafers with or without TSVs, including post final metal temporary bonding, wafer thinning, TSV formation and reveal, micro-bumping, redistributed line (RDL) formation and carrier de-bond. SEMI 3DS-IC Standards Activities - September 2012

  23. Task Force Overview • New! Middle-End Process Task Force (cont’d) • Scope: • Identify and suggest generic process flow for middle-end process. • Develop criteria for micro-bump dimensions, planarization and related. Dimensions can be determined into wafer-to-wafer level (WWL), die-to-wafer level (DWL), and die-to-die level (DDL). • Develop criteria for TSV CMP process and related. The via size, via surface roughness, post CMP Cu step height, and post CMP Cu bump planarization uniformity are a few of the related planarization criteria that will be critical to the micro bumping yield and inspection standard. • Develop standard for photo alignment mark and overlay mark. Alignment marks for patterning TSVs and stacking devices/wafers would be standardized for recognition. • Suggest wafer or die thickness variation and warpage before and after MEOL and identify thickness variation, void size, overall void percentage of temporary bonding glue layer, warpage control after temporary bonding and corresponding measure method. • Develop TSV quality criteria such as thickness uniformity, TSV depth variation, void, pattern density, TSV metal extrusion. • Research on in-process testing. SEMI 3DS-IC Standards Activities - September 2012

  24. SNARFs(Standards New Activity Report Form) SEMI 3DS-IC Standards Activities - September 2012

  25. SNARF # 5473 • New Standard: Guide for Alignment Mark for 3DS-IC Process • Task Force: Middle-End Process TF • Rationale: • To ensure consistent precise alignment of layers, chips and wafers, the photo alignment mark configuration is the key and should be developed. Therefore, the guide will provide alignment mark strategy for die to die, die to wafer, and wafer to wafer stacking. This guide will address the universal alignment mark where the outcome will be a feasible photo alignment standard. • Scope: • Define and develop litho alignment strategy for die to die (DDL), die to wafer (DWL) and wafer to wafer (WWL) stacking. The alignment mark is preferred to be implemented at front side final metal and/or backside metal layer masking. This guide will address universal alignment mark, including shape, dimension, and location will be proposed. The outcome of a feasible photo alignment standard will be critical to the DDL, DWL and WWL stacking. SEMI 3DS-IC Standards Activities - September 2012

  26. SNARF # 5474 • New Standard: Guide for CMP and Micro-bump Processes for Frontside TSV Integration • Task Force: Middle-End Process TF • Rationale • To speed up the volume production of 3DS-IC products, a generic middle-end process flow is needed to communicate the frontend and backend processes. The quality criteria and metrology methodology of the key modules such as TSV, CMP and micro-bump are developed to ensure the high yield of the middle-end process. Therefore, this guide will suggest generic middle-end process flow to define acceptable TSV and CMP quality criteria, and develop methodology and measuring procedure for micro-bump. The guide will provide criteria and common baselines of the middle-end process for related upstream and downstream manufacturers in fabricating the 3DS-IC products. • Scope • Propose a frontside TSV integration scheme as one of the generic middle-end process flow. The flow includes steps such as TSV formation, RDL formation, CMP, temporary carrier bonding, wafer thinning, micro-bump formation, carrier debonding, etc. • Define acceptable CMP criteria of TSV in terms of dishing, erosion, and voids. CMP criteria can be determined by metrology technology such as Alpha stepper, Ultrasonic, Coherence Interferometry, and etc. TSV formation and reveal are significantly dependent on the performance of CMP process. The outcome of the high CMP quality yields better TSV connectivity. • Develop criteria for measurement methodology for micro-bump dimensions, including sampling rate, sampling sites and mapping, reference datum, and survey available metrology tools. The outcome will be an important bridge communication between IC design firms and associated foundry and packaging fabs. The assumption of DWL and DDL are that testing data is available for known good die status. SEMI 3DS-IC Standards Activities - September 2012

  27. Thank you! • For more information or to participate in any Taiwan 3DS-IC activities, please contact: • Catherine ChangTaiwan Standards & Technologycchang@semi.org SEMI 3DS-IC Standards Activities - September 2012

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