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Asynchronous comparator design

Asynchronous comparator design. Motivation Background: Sync and Async comparators Delay-insensitive carry-lookahead comparators Complexity Analysis Conclusions. Motivation. Comparison is one of the most important operations in digital systems.

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Asynchronous comparator design

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  1. Asynchronous comparator design • Motivation • Background: Sync and Async comparators • Delay-insensitive carry-lookahead • comparators • Complexity Analysis • Conclusions

  2. Motivation • Comparison is one of the most important • operations in digital systems. • Comparators are used in ALUs, cache memory, • MMU and data hazard detection. • Integer comparison: use an integer adder. • Problem: addition time > comparison time. • High speed comparison is needed.

  3. Background: Binary Comparison • Worst case: A=B • A: 01101110 • B: 01101110 • Best case: A>B • A: 01101110 • B: 10101110 • Comparators can perform average case behavior

  4. Background • Ripple-Carry Comparator(Sync): • Flow table specification:

  5. Background • Delay-Insensitive Ripple-Carry Comparator: • Flow table:

  6. Background • Ripple-Carry Comparator: • Logic complexity: O(n) • Time complexity: O(n) • Delay-Insensitive Ripple-Carry Comparator: • Logic complexity: O(n) • Time complexity: O(1)

  7. Carry-Lookahead Comparators • RCC requires n stage-propagation delays. • Use carry-lookahead comparators(CLC). • CLCs: • Logic complexity: O(n) • Time complexity: O(log n)

  8. 8-bit carry-lookahead comparator

  9. DI Carry-Lookahead Comparator • Delay-Insensitive Carry-Lookahead Comparators • may be implemented by using delay-insensitive • code. • 1. dual-rail signaling: input bits • 2. one-hot code: internal signals, s, g, e (S, G, E). • S: smaller (A<B) • G: greater (A>B) • E: equal (A=B)

  10. CMOS Implementation • DI P-module:

  11. CMOS Implementation • DI I-module:

  12. CMOS Implementation • DI SI-module: 3 2-input AND gates.

  13. CMOS Implementation • Speed-up circuits for S and G signals: • Dynamic OR • gates.

  14. CMOS Implementation • Speed-up circuits for E signals: • Dynamic OR gate:

  15. SPICE Simulation: • SPICE Simulation contains two parts: • Random number inputs: • 10000 random generated input pairs • Statistical data: • running examples on a 32-bit ARM • emulator

  16. SPICE Simulation: • Random number inputs: • 10000 random generated input pairs • a. RCC: 32.4ns • b. CLC: 6.2ns

  17. SPICE Simulation: • Confidence Limits:

  18. SPICE Simulation: • Confidence Limits:

  19. SPICE Simulation: • Distribution of typical-case comparisons:

  20. SPICE Simulation: • SPICE simulation • results: • dynamic traces

  21. Conclusions • A new pratical design of DI comparator. • Theoretically, • Logic Complexity:((n)). • Time Complexity:((1)). • Reality: • more than 2 times faster than its sync • counterpart with 80% usable clock. • Suitable for VLSI implementation.

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