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FLIP FLOPS

FLIP FLOPS. Prepared by: Careene McCallum-Rodney. INTRODUCTION TO FLIP FLOPS. These are sequential circuits that use a clock (which is asynchronous) to regulate the inputs to each circuit. This gives the circuit time to process the input and give the required results (propagation delay ).

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FLIP FLOPS

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  1. FLIP FLOPS Prepared by: Careene McCallum-Rodney

  2. INTRODUCTION TO FLIP FLOPS These are sequential circuits that use a clock (which is asynchronous) to regulate the inputs to each circuit. This gives the circuit time to process the input and give the required results (propagation delay).

  3. The flip flops to be focused on are: • SR Flip Flop using NAND Latch and NOR Latch. • Data Flip Flop • JK Flip Flop • Toggle Flip Flop

  4. SR FLIP FLOPS • SR Flip Flops can be implemented using a NAND latch or a NOR latch. • The input values will have to be combined with the clock pulse. When the clock pulse is high, that is when data can go through.

  5. SR FLIP FLOPS • The flip flop knows a set state when the S=1 and R= 0 and the reset state is known as S=0 and R=1, no matter what latch is used. • Therefore when the clock is on a high the gate used to send in the data should bare in mind the latch being implemented (because the NAND latch works on an active low and a NOR latch works with a high). • Also, a set is defined as the output—Q, giving a value of 1 and a reset state is defined as the output—Q , giving a value of 0.

  6. SR Flip Flop using NOR Latch

  7. SR Flip Flop using NAND Latch

  8. Characteristic Table for SR Flip Flop • The Characteristic table for both is the same. • Characteristic Table

  9. The flip flops to be focused on are: • SR Flip Flop using NAND Latch and NOR Latch. • Data Flip Flop • JK Flip Flop • Toggle Flip Flop

  10. DATA FLIP FLOP In the previous flip flop, two things are recognized: ·  S=R=0 means the output will be maintained. This can be done by means of the clock being on a low. ·  S=R=1means that the output will be unstable. The two above states are not needed. We can get rid of them by ensuring that R is the complement of S.

  11. Data Flip Flop (using NOR Latch)

  12. Data Flip Flop (using NAND Latch)

  13. Truth Table for the D Flip Flop

  14. The flip flops to be focused on are: • SR Flip Flop using NAND Latch and NOR Latch. • Data Flip Flop • JK Flip Flop • Toggle Flip Flop

  15. J K FLIP FLOP In the SR Flip Flop circuit, there is a set of inputs that will not be used – S =1 and R=1. It would be good to use these inputs, instead of having them not in use.

  16. Basic J K Flip Flop

  17. J K FLIP FLOP with input S=R=1 • In the JK Flip Flop, when the clock is on a high and a series of J=K=1 a race will take place.

  18. Characteristic Table for JK Flip Flop

  19. The flip flops to be focused on are: • SR Flip Flop using NAND Latch and NOR Latch. • Data Flip Flop • JK Flip Flop • Toggle Flip Flop

  20. Toggle Flip Flop The Toggle Flip Flop uses a JK Flip Flop. The J and K will always have the same value. The toggle takes place when the clock is on a HIGH and J=K=1 (i.e. T =1).

  21. Toggle Flip Flop

  22. Behaviour of Toggle FF If the previous output =1 and T = 0 - memory is maintained If the previous output =0 and T = 0 - memory is maintained If the previous output =1 and T = 1 - the output is 0 If the previous output =0 and T = 1 - the output is 1

  23. Truth Table for Toggle FF

  24. THE END

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