Flip-Flops
This guide covers flip-flops, focusing on D-type and J-K configurations, including how they function with clock signals (CLK) and their behavior during transitions. It explains the operations of positive edge-triggered D Flip-Flops, pulse-narrowing circuits, and the master-slave arrangement. You will learn about latch behavior, setup and hold times, and the implications of clock edges on the output. This fundamental understanding is essential for digital circuit design and implementation.
Flip-Flops
E N D
Presentation Transcript
Flip-Flops Section 4.3 Mano & Kime
D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 D Latch S !S D Q CLK !Q !R R Note that Q follows D when the clock in high, and is latched when the clock goes to zero.
D Pulse-narrowing circuit CLK D NCK Q !Q D CLK Q !Q 0 1 0 1 1 1 1 0 X 0 Q0 !Q0 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop S !S Q NCK !Q !R R
D Q CLK !Q D CLK Q !Q 0 0 1 1 1 0 X 0 Q0 !Q0 D Flip-Flop Positive edge triggered D gets latched to Q on the rising edge of the clock.
D Q CLK !Q D Flip-Flop pulse width CLK setup time hold time y z propagation delay
Making a positive edge-triggered D Flip-Flop from Master-Slave D Latches x y z input output D Q D Q master slave CLK’ E E CLK CLK CLK’ x y z
SR Master-Slave Flip-Flop S R CLK Q !Q 0 0 1 Q0 !Q0 Store 0 1 1 0 1 Reset 1 0 1 1 0 Set 1 1 1 1 1 Disallowed X X 0 Q0 !Q0 Store
J-K Flip-Flop J K CLK Q !Q 0 0 Q0 !Q0 0 1 0 1 1 0 1 0 1 1 Toggle X X 0 Q0 !Q0 J Q CLK !Q K
