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Nios II Processor-Based Self-Adaptive QRS Detection System

Nios II Processor-Based Self-Adaptive QRS Detection System. Institution: Indian Institute of Technology, Kharagpur Participants: Sai Prashanth , Prashant Agrawal Instructor: Professor Agit Pal. Outline. Background Project Outline FPGA Design Signification Functional Description

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Nios II Processor-Based Self-Adaptive QRS Detection System

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  1. RPR Nios II Processor-Based Self-Adaptive QRS Detection System Institution: Indian Institute of Technology, Kharagpur Participants: SaiPrashanth, PrashantAgrawal Instructor: Professor Agit Pal

  2. Outline RPR • Background • Project Outline • FPGA Design Signification • Functional Description • Plot Architecture • QRS Detection Results • ECG Hardware Block Diagram • Software QRS Detection Algorithm Flow Chart • Design’s Implementation steps • Conclusion

  3. Background RPR • QRS detection provides the fundamental for almost all ECG analysis algorithm • Software QRS detection • Based on signal processing techniques • An asymptotic detection performance • Choosing the QRS detection algorithm best suited to the current context is an essential step in the development of a real-time ECG analysis system

  4. Project Outline RPR • Algorithm-bank-based solutions • Periodic sampling of the input ECG signal • Dynamic decision to find the most appropriate algorithm Reduction of the number of errors Patient Context Sub-units within the scope of this project SAMPLER AlteraNios II Processor (CPU0) ECG ADC ANALYZER AlteraNios II Processor (CPU1) Arrhythmia Fig.2: The design overview of ECG monitoring system

  5. Project Outline RPR Patient Context Acquisition, context analysis, and piloting of the analyzer SAMPLER AlteraNios II Processor (CPU0) ECG ADC Arrhythmia ANALYZER AlteraNios II Processor (CPU1) • The actual QRS complex detection and medical diagnosis Fig.2: The design overview of ECG monitoring system • Implemented using the AlteraNios®II processor

  6. FPGA Design Significance RPR • The trend in embedded system design • Implementing entire functional system on a single chip • The advent of high-density FPGA have enabled designers to implement a complete system on a chip • Benefits • Portable, cost effective, and low power consumption (compared to PCs) • Complex ICs with millions of gates are now available • Performing control and decision making operation efficiently • Performing DSP operations and other computationally intensive tasks • SOPC Builder integrates complex system components such as IP blocks, memories, and interfaces to off-chip devices • The AlteraNios II processor supports HW/SW co-designand multi-core processing

  7. Functional Description RPR Patient Context Rule Base SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  8. Functional Description RPR Patient Context Rule Base Temporal abstraction is composed of four linked tasks SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  9. Functional Description RPR Patient Context Rule Base Four tasks are performed by shortest path (SP) algorithm SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  10. Pilot Architecture RPR Current Context Context Manager Arrhythmia Recognition Level Interface Engine Chronicle Models to Use Line Context Chronicle Model Choice Rules Temporal Abstraction Tasks Level Interface Engine Task to Activate and Deactivate Patient Context Task ChoiceRules Arrhythmia Context SP Algorithm Level Interface Engine SP Algorithm to Tune SP Piloting Rules Manager Rules

  11. QRS Detection Results RPR Five ECGs were generated from the MIT-BIH database Ne: The number of errors Er : The error rate (Er = Ne/NQRS, where NQRS is the total number of actual QRSs) • The pilot chooses the best algorithm with the aid of the piloting rules • In this study, the algorithm thresholds are optimal in the sense that Ne is minimum

  12. ECG Hardware Block Diagram RPR ADC ECG Data ANALYZER (Nios II Processor Augmented with Custom Instructions) RAM LCD Display SAMPLER (NiosCoprocesspr) Keyboard LCD Data Buffer Interrupt

  13. Software QRS Detection Algorithm Flow Chart RPR Selection of Characteristic Scales Determination of Modulus Maxima Lines of R Waves Elimination of Redundant Modulus Maxima Lines Calculation of Singular Degree Detection of R Peak QRS Onset & Offset Detection Elimination of Isolated Modules Maxima Lines T & P Wave Detection

  14. Design’s Implementation Steps RPR • Research and determine a set of complementary QRS detection algorithms anddevelop software algorithms to support them • Create a Quartus II projectCompile and debug the project and review the compilation report and test the project • Create an algorithm bank consisting of four different QRS detection algorithms and test the performance

  15. Design’s Implementation Steps RPR • Update the SOPC Builder processor configuration and optimize the processor until the desired performance requirement is met • Create interrupt-based interfaces using Nios II IDE and test these I/O interface • Test the ECG medical monitoring system performance and determine the error rates of the QRS complex detection

  16. Applying SOPC Concepts RPR • Compared to ASIC SOC, SOPC has many unique features • The design uses SOPC concepts in the following ways • Modular system design • The system is divided and simplified, which makes it easer to implement • System integration • - It is very difficult to implement highly integrated design without lowering the design target or using a different FPGA • Various modes • Using SOPC concepts and excellent design tools enabled authors to use various mode • Final system can be updated • The design can be flexible configured and updated during the design process

  17. Conclusion RPR • Using Nios II processor, it is possible to design their system easily, including dual-core embedded processors, on-chip and off-chip memory, and high-speed I/O ports • Using SOPC Builder, it is possible to modify the CPU hardware at any time for multi-purpose development • Altera’s ability to develop and update the Nios II processor and function was extremely important • Using SOPC concepts allowed us to create a more flexible, dynamically reconfigurable, and computationally intensive implementation

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  19. Functional Description RPR Patient Context Rule Base Separating the actual ECG signal from the noisy part of the signal SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  20. Functional Description RPR Patient Context Rule Base Identifying QRS occurrence dates SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  21. Functional Description RPR Patient Context Rule Base Labeling QRS morphologies SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

  22. Functional Description RPR Patient Context Rule Base Identifying P wave occurrence dates SAMPLER (Nios II Processor, CPU0) Line Context Analyzer Arrhythmia Context Analyzer ADC PILOT ECG ANALYZER (Nios II Processor, CPU1) Temporal Abstraction Chronicle Recognition Filtering QRS Classification Arrhythmia QRS Detection P-wave Detection Algorithm Bank Chronicle Base Fig.3: ECG Medical Monitoring System

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