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Automating analog circuit design

Automating analog circuit design. Dave Colleran October, 2001. Outline. Barcelona’s core technology Geometric program (GP) form Transistor models Two-stage opamp Clock synchronization PLL. Core technology.

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Automating analog circuit design

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  1. Automating analog circuit design Dave Colleran October, 2001

  2. Outline • Barcelona’s core technology • Geometric program (GP) form • Transistor models • Two-stage opamp • Clock synchronization PLL

  3. Core technology Complex circuit behavior is modeled accurately in a form compatible with geometric programming. Geometric programs can be solved very efficiently.

  4. Geometric programming (background) • A family of optimization problems, not a specific algorithm • Used in engineering since 1967 (Duffin, Peterson, Zener) • Used for digital transistor sizing with Elmore delay since the 1980’s (Fishburn & Dunlap’s TILOS)

  5. Monomial functions vector of positive variables • a monomial function g has the form where . Example:

  6. Posynomial functions • a posynomial function f is a sum of monomials • Example:

  7. Geometric Program • where are posynomial and are monomial • can be transformed into a nonlinear but convexproblem

  8. Solving GP’s Use of interior-point methods for GP: • are extremely fast • find globally optimal solution (independent of starting point) or provide proof of infeasibility • based on Newton’s method applied to barrier functions that trap the solution in interior of feasible region

  9. Transistor Models GP1 transistor model: • Gate-overdrive voltage: • Saturation condition: • Transconductance: • Output conductance: • Capacitances:  monomial  monomial  monomial  posynomial where are technology-dependent constants.

  10. Accurate Transistor models (Complex)

  11. Two-stage opamp • 15 design variables: W’s, L’s, R, Cc, Ibias

  12. Basic Specifications • Limits on device sizes • Maximum quiescent power • Maximum area

  13. Small-signal specifications • Minimum open-loop DC gain • Minimum unity-gain bandwidth

  14. Small-signal specifications • Phase margin

  15. Op-amp design • 0.35 m CMOS process (TSMC thru. MOSIS) • Two stage op-amp • Sizing: 1 minute (3 corners), no tweaking after optimization • Simulation: 5 minutes

  16. Op-amp Array

  17. Clock synchronization PLL

  18. Charge pump schematic

  19. VCO schematic

  20. Hierarchical design • Total power consumption • Peak jitter: CP mismatch and VCO phase noise • Charge pump

  21. Hierarchical design (cont) • VCO (Hajimiri, JSSC 1998) • Total (VCO+CP)

  22. VCO small-signal model for PSRR

  23. Where: VCO small-signal model (cont) Model Simulation

  24. Specific PLL design example • TSMC 0.25um, 2.5V process • Duty cycle requires divide by 2 • Peak jitter -> 3 sigma • Very tight low freq. power supply rejection spec. • 2MHz crossover frequency

  25. Test results

  26. Test results Jitter histogram, 50MHz out 50MHz duty cycle

  27. Summary Combining optimization technology with analog expertise features: • automatic, fast, and optimal • process independent • specification driven, GDSII output • scalable to large blocks (e.g., PLL, ADC, …) limitations: • cannot invent new circuit topologies • large effort to put analog cell in optimization form

  28. Extra slides

  29. Geometric Program in Convex Form Let : • is convex function of y • is affine function of y

  30. PFD schematic

  31. PFD static phase error – manual design

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