SHARC instruction set

1. SHARC instruction set • SHARC programming model. • SHARC assembly language. • SHARC memory organization. • SHARC data operations. • SHARC flow of control. • SHARC instructions may use algrebraic notation and has several parts. • See my homepage for “SHARC User Manual” Overheads for Computers as Components

2. ADSP-2106x SHARC Block Diagram Overheads for Computers as Components

3. * Computation Units Overheads for Computers as Components

4. SHARC programming model • Register files: • R0-R15 (aliased as F0-F15 for floating point) • 40 bits long and 32 bit data at the most significant location • Status registers. • ASTAT[0..31], STKY[0..31], MODE1[0..31] • Loop registers. • Data address generator (DAG) registers. • Interrupt registers. Overheads for Computers as Components

5. SHARC assembly language • Algebraic notation terminated by semicolon: R1=DM(M0,I0), R2=PM(M8,I8); ! comment label: R3=R1+R2; data memory access program memory access Overheads for Computers as Components

6. SHARC memory space: evenly split between PM & DM Different word sizes for instructions (48 bits), basic data word (32 bits), address (32 bits) short word addressing 0x40000 normal word addressing 0x20000 interrupt vectors forbidden 256 IOP registers 0x0 Overheads for Computers as Components

7. SHARC data types • 32-bit IEEE single-precision floating-point. • 40-bit IEEE extended-precision floating-point. • 32-bit integers. • Memory organized internally as 32-bit words. Overheads for Computers as Components

8. SHARC microarchitecture • Modified Harvard architecture: DM + PM • Program memory can be used to store some data. • Register file connects to (CPU’s 3 major functions): • multiplier • shifter; • ALU. Overheads for Computers as Components

9. SHARC mode registers • Most important ones for data operations: • ASTAT: arithmetic status. • STKY: sticky (version of some bits in ASTAT) • MODE 1: mode 1. Overheads for Computers as Components

10. Rounding and saturation • Floating-point can be: • rounded toward zero; • rounded toward nearest. • MODE1 bits control the rounding mode • ALU supports saturation arithmetic on fixed-point values (ALUSAT bit in MODE1). • Overflow results in max value, not rollover. Overheads for Computers as Components

11. Multiplier • Fixed-point operations can accumulate into localMR register (manipulate there) or be written to register file. • Fixed-point result is 80 bits. • Floating-point results always go to register file. • Status bits (0, 5, 6, 7, 8, 9 bits) in ASTAT reg: ALU result 0 or floating-point underflow (AZ), floating-point invalid (AI),negative (MN), under (MU), overflow (MV), invalid (MI), Overheads for Computers as Components

12. MULTIPLIER • Perform both fixed- and floating-point multiplication • Saturation, rounding and setting the result 0 Overheads for Computers as Components

13. ALU/shifter status flags ALU: • Zero (AZ), overflow (AV), negative (AN), fixed-point carry (AC), input sign, floating-point invalid (AI), last op was floating-point, compare accumulation registers, floating-point under/overflow, fixed-point overflow, floating-point invalid Shifter: • Zero (SZ), overflow (SV), shifter input sign (SS) in ASTAT reg Overheads for Computers as Components

14. ASTAT Register Overheads for Computers as Components

15. Flag operations • All ALU operations set AZ (zero), AN (negative), AV (overflow), AC (fixed-point carry), AI (floating-point invalid) bits in ASTAT. • STKY is sticky version of some ASTAT bits. • Sticky bits set along with the ASTAT bits, but are not cleared. Remains set until cleared by an instruction Overheads for Computers as Components

16. STKY Register Overheads for Computers as Components

17. Example: data operations • Setting of ASTAT bits • Fixed-point -1 + 1 = 0: • AZ = 1, AU = 0, AN = 0, AV = 0, AC = 1, AI = 0. • STKY bit AOS (fixed point overflow) not set, retain its value • Fixed-point -2*3: • MN = 1, MV = 0, MU = 0, MI = 0. • Four STKY bits, none of them set. • MOS (mult. fixed-point overflow), MVS (floating-point overflow), MUS (mult. floating point underflow), MIS (mult. floating-point invalid operation) • LSHIFT 0x7fffffff BY 3: SZ=0,SV=1,SS=0. • Shifter has no sticky bits Overheads for Computers as Components

18. Multifunction computations • Can issue some computations in parallel: (p. 99) • dual add-subtract; • fixed-point multiply-accumulate and add,subtract,average • floating-point multiply and ALU operation • multiplication and dual add/subtract • Multiplier operandsfrom R0-R7 • One from R0-R3, the other from R4-R7 • ALU operands from R8-R15. • One from R8-R11, the other from R12-R15 • Ex) R6 = R0 * R4, R9 = R8 + R12, R10 = R8 - R12 Overheads for Computers as Components

19. SHARC load/store • Load/store architecture: no memory-direct operations. • Two data address generators (DAG1, DAG2): • program memory; • data memory. • 2 load-stores / cycle is possible • Must set up DAG registers to control loads/stores. • Set up several registers to perform a load or store • After setup, DAG hardware automatically updates their values so that a series of accesses can be performed • DAG is esp. useful for the sequential accesses in array arithmetic found in DSP programs Overheads for Computers as Components

20. MODE 1 DAG1 registers Overheads for Computers as Components

21. Each DAG • Has eight sets of primary registers • Quick access to multiple sets of data • E.g. multiplication of two arrays Overheads for Computers as Components

22. Data address generators Provide indexed, modulus, bit-reverse indexing. MODE1 bits determine whether primary or alternate registers are active. Overheads for Computers as Components

23. BASIC addressing modes provided by DAGs • Immediate value: R0 = DM(0x20000000); • Direct load: R0 = DM(_a); ! Loads contents of _a • Direct store: DM(_a)= R0; ! Stores R0 at _a • Absolute addressing • Entire address in the instruction Overheads for Computers as Components

24. Post-Modify with update • I register holds base address. • M register/immediate holds modifier value. R0 = DM(I3,M3) ! Load DM(I2,1) = R1 ! Store I register is updated by the modifier Overheads for Computers as Components

25. Base-plus-offset • RO=DM(M1,I0) ; we can mix any M with any I as long as both are in the same DAG • Note the difference: R0 = DM(I0, M1) Overheads for Computers as Components

26. Pre-Mod vs Post-Mod Overheads for Computers as Components

27. Circular Buffer • Circular buffer: L register is buffer length, B is buffer base address. (Li and Bi loaded together) • L as number of locations is +, > 0; • I = B initially; and • I is used in post-modify mode and the incremented I value is compared to the sum of B + L. if the end is reached, I is wrapped around. Overheads for Computers as Components

28. DAG – bit-reversal addressing • Useful in FFT. • Can be performed only in I0 & I8 • Controlled by BR0 & BR8 bits in MODE1 reg Overheads for Computers as Components

29. 24bits 32bits Overheads for Computers as Components

30. Data in program memory • Can put data in program memory to read two values per cycle: F0 = DM(M0,I0), F1 = PM(M8,I9); • Compiler allows programmer to control where memory values are stored in. • float dm a[N] • float pm b[N] Overheads for Computers as Components

31. Example: C assignments • C: x = (a + b) - c; • Assembler: R0 = DM(_a) ! Load a R1 = DM(_b); ! Load b R3 = R0 + R1; R2 = DM(_c); ! Load c R3 = R3-R2; DM(_x) = R3; ! Store result in x Overheads for Computers as Components

32. Example, cont’d. • C: y = a*(b+c); • Assembler: R1 = DM(_b) ! Load b R2 = DM(_c); ! Load c R2 = R1 + R2; R0 = DM(_a); ! Load a R2 = R2*R0; DM(_y) = R2; ! Store result in y Overheads for Computers as Components

33. Example, cont’d. • Shorter version using pointers (i.e. I regs): ! Load b, c R2=DM(I1,M5), R1=PM(I8,M13); R0 = R2+R1, R12=DM(I0,M5); R6 = R12*R0(SSI); DM(I0,M5)=R6; ! Store in y Overheads for Computers as Components

34. Overheads for Computers as Components

35. Example, cont’d. • C: z = (a << 2) | (b & 15); • Assembler: R0=DM(_a); ! Load a R0=LSHIFT R0 by #2; ! Left shift R1=DM(_b); R3=#15; ! Load immediate R1=R1 AND R3; R0 = R1 OR R0; DM(_z) = R0; Overheads for Computers as Components

36. SHARC 21061 program sequencer Manage Program Structures • Loops. One sequence of instructions is executed several times with zero overhead. • Subroutines. The processor temporarily interrupts sequential flow to execute instructions from another part of program memory. • Jumps. Program flow is permanently transferred to another part of program memory. • Interrupts. A special case of subroutines in which the execution of the routine is triggered by an event that happens at run time, not by a program instruction. • Idle. A special instruction that causes the processor to cease operations, holding its current state. When an interrupt occurs, the processor services the interrupt and continues normal execution. Overheads for Computers as Components

37. SHARC 21061 program sequencer • Selects the address of the next instruction • Performs a wide range of related functions, such as: • incrementing the fetch address, • maintaining stacks, • evaluating conditions, • decrementing the loop counter, • calculating new addresses, • maintaining an instruction cache, and • handling interrupts. Overheads for Computers as Components

38. Overheads for Computers as Components

39. Due to pipelining, writes to some of these registers do not take effect on the next cycle; for example, if you write the MODE1 register to enable ALU saturation mode, the change will not occur until two cycles after the write. Also, some registers are not updated on the cycle immediately following a write; it takes an extra cycle before a read of the register yields the new value. Table 3.1 summarizes the number of extra cycles for a write to take effect (effect latency) and for a new value to appear in the register (read latency). A “0” indicates that the write takes effect or appears in the register on the next cycle after the write instruction is executed. A “1” indicates one extra cycle. Overheads for Computers as Components

40. Conditional instructions Instructions may be executed conditionally. Conditions come from: • arithmetic status (ASTAT); • mode control 1 (MODE1); • flag inputs; • loop counter. Overheads for Computers as Components

41. SHARC jump • Unconditional flow of control change: JUMP foo • Three addressing modes: • Direct : instruction specifies a 24-bit address in the immediate format ; PC  immediate • Indirect : DAG2 supplies the address • PC-relative : PC  PC + immediate [specified in the instruction] Overheads for Computers as Components

42. Branches • Types: CALL, JUMP, RTS, RTI. • Can be conditional. E.g. conditional JUMP • Address can be direct, indirect, PC-relative. • Can be delayed or non-delayed. • JUMP causes automatic loop abort. See “Program Sequencing 3.4” in the Sharc user manual A return causes the processor to branch to the address stored at the top of the PC stack. There are two types of returns: return from subroutine (RTS) and return from interrupt (RTI). The difference between the two is that the RTI instruction not only pops the return address off the PC stack, but also: 1) pops the status stack if the ASTAT and MODE1 status registers have been pushed (if the interrupt was IRQ2-0, the timer interrupt, or the VIRPT vector interrupt), and 2) clears the appropriate bit in the interrupt latch register (IRPTL) and the interrupt mask pointer (IMASKP). Overheads for Computers as Components

43. Example: C if statement • C: if (a > b) { x = 5; y = c + d; } else x = c - d; • Assembler: ! Test R0 = DM(_a); R1 = DM(_b); COMP(R0,R1); ! Compare IF GE JUMP fblock; Overheads for Computers as Components

44. C if statement, cont’d. ! True block tblock: R0 = 5; ! Get value for x DM(_x) = R0; R0 = DM(_c); R1 = DM(_d); R1 = R0+R1; DM(_y)=R1; JUMP other; ! Skip false block Overheads for Computers as Components

45. C if statement, cont’d. ! False block fblock: R0 = DM(_c); R1 = DM(_d); R1 = R0-R1; DM(_x) = R1; other: ! Code after if Overheads for Computers as Components

46. Fancy if implementation • C: if (a>b) y = c-d; else y = c+d; • Use parallelism to speed it up---compute both cases, then choose which one to store. Overheads for Computers as Components

47. Fancy if implementation, cont’d. ! Load values R1=DM(_a); R2=DM(_b); R3=DM(_c); R4=DM(_d); ! Compute both sum and difference R12 = R2+R4, R0 = R2-R4; ! Choose which one to save COMP(R2,R1); if GE R0=R12; DM(_y) = R0 ! Write to y Overheads for Computers as Components

48. Termination condition Loop length Last instruction in loop DO UNTIL loops DO UNTIL instruction provides efficient looping (zero overhead): LCNTR=30, DO label UNTIL LCE; R0=DM(I0,M0), F2=PM(I8,M8); R1=R0-R15; label: F4=F2+F3; Overheads for Computers as Components

49. Example: FIR filter • C: for (i=0, f=0; i<N; i++) f = f + c[i]*x[i]; Overheads for Computers as Components

50. FIR filter assembler ! Loop setup I0=_a; M0=1; I8=_b; M8=1; ! Set up increments ! Loop body LCNTR=N, DO loopend UNTIL LCE; ! Use postincrement mode R1=DM(I0,M0), R2=PM(I8,M8); loopend: R8=R1*R2; R12=R12+R8; !Mul & Acc Overheads for Computers as Components