AT91RM9200 Embedded Peripherals
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Presentation Transcript
External Bus Interface • Integrates three external memory controllers • Static Memory Controller, SDRAM Controller and Burst Flash Controller • Additional logic for SmartMedia and CompactFlash support • Optimized external bus • 16 or 32-bit data bus • Up to 26-bit address bus, up to 64M Bytes addressable • Up to 8 chip selects • Optimized pin multiplexing to reduce latencies on external memories
External Bus Interface • Block Diagram
External Bus Interface • Static Memory Controller • External memory mapping, 512M Bytes address space • Up to 8 chip select lines • 8 or 16-bit data bus • Byte write or Byte select lines • Remap of Boot Memory • Programmable wait state generation, Data float time, Setup time Read/Write, Hold time Read/Write • Compliant with LCD Module • External Wait Request
External Bus Interface • SDRAM Memory Controller • External memory mapping, 256M Bytes address space • Supports an SDRAM with two or four internal banks • Supports an SDRAM with 16 or 32-bit data path • Automatic refresh operation, refresh rate is programmable • Supports self-refresh and low-power modes • Read or Write burst length of one location • Word, Half-word, Byte access • Multibank Ping-pong access • SDRAM power-up initialization by software • Refresh error interrupt
External Bus Interface • Burst Flash Controller • 16-bit data bus • Asynchronous or Burst mode read Byte, Half-word or Word accesses • Asynchronous mode Half-word write accesses • Programmable data access time • Programmable latency after output enable • Programmable Burst Flash clock rate • Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled • Multiplexed or Separate address and data buses
External Bus Interface • Compact Flash • I/O mode : used for I/O peripherals like modems • Attribute memory mode : (0 -> 1FF) contains the card ID, manufacturer ID … • Common memory mode : allows to store data in memory • True IDE mode is not supported
Power Management Controller • PMC embeds and controls • One main oscillator providing a frequency range [3 : 20] MHz • One slow clock oscillator (32768 Hz) • Two phase locked loops and dividers • Clock prescalers • PMC provides clocks to the whole system • Processor clock PCK : typically MCK but switched off when entering idle mode. • Master clock MCK, it is available to the modules running permanently • USB clocks UHPCK and UDPCK at 48MHz
Power Management Controller • Four operating modes • Normal : processor and peripheral clocks are enabled • Idle : processor clock is disabled, waiting for interrupt, Peripheral clocks are enabled • Slow : processor and peripherals run at slow clock • Standby : combination of slow clock mode and idle mode.
Power Management Controller • Block Diagram
Advanced Interrupt Controller • AIC controls the interrupt lines of an ARM processor • Thirty-two individually maskable and vectored interrupt sources • Source 0 is reserved for the fast interrupt input • Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU …) • Sources 2 to 31 control up to thirty embedded peripheral interrupts or external interrupts. • Programmable Edge-triggered or Level-sensitive internal sources • Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive external sources • AIC enables/disables independently the thirty-two sources
Advanced Interrupt Controller • Eight-level priority controller • Handles priority of the interrupt sources 1 to 31, the fast interrupt logic of the AIC has no priority controller • Higher priority interrupts can be served during service of lower priority interrupt
Advanced Interrupt Controller • Vectoring • One 32-bit vector register per interrupt source, fast interrupt included • Interrupt vector register reads the corresponding current interrupt vector (handler address) • Branch in one single instruction to the right handler
Advanced Interrupt Controller • Fast forcing • Redirects any normal interrupt source on the fast interrupt of the processor • Unlike IRQs and FIQs, fast forced interrupts aren’t cleared automatically • General interrupt mask • Prevents interrupts from reaching the processor • Processor can still be waken up even if the mask is set up • Provides processor synchronization on events without having to handle an interrupt
Advanced Interrupt Controller • Interrupt nesting • Handles a high priority interrupt during the service of a lower priority interrupt • Current priority interrupt is pushed in an 8-level wide, embedded hardware stack • Protect mode • Allows to read the interrupt vector register without performing the associated automatic operations : stacking and clearing • This is necessary when working with debug • Interrupt stacking is performed by writing to the interrupt vector register
Advanced Interrupt Controller • Spurious interrupt • Spurious vector is returned when the assertion of an interrupt does no longer exists when the IVR is read • Application Block Diagram
Peripheral Data Controller • PDC transfers data between on-chip serial peripherals and on- and off-chip memories. • On-chip serial peripherals UART, USART, SSC, SPI, MCI • Using PDC avoids processor intervention and removes interrupt-handling overhead
Peripheral Data Controller • Two PDC Channels for Each peripheral • Receive Channel • Trigger = RXRDY • End of Transfer = ENDRX • Rx Buffer Full = RXBUFF • Transmit Channel • Trigger = TXRDY • End of Transfer = ENDTX • Tx Buffer Empty = TXBUFE Trigger USART PDC Receive Channel Status Size = Byte Triger PDC Transmit Channel Status Size = Byte
Tx Pointer US_TPR US_TNPR Tx Next Pointer US_TNCR/TCR Tx Next Counter Tx Counter Rx Pointer US_RPR Rx Next Pointer US_RNPR Rx Next Counter Rx Counter US_RNCR/RCR Peripheral Data Controller • A PCD channel’s user interface is integrated in the memory space of each peripheral • A 32-bit memory pointer register • A 16-bit transfer count register • A 32-bit register for next memory pointer • A 16-bit register for next transfer count
Multimedia Card Interface • Supports MultiMediaCard specification version 2.2 • Supports SD Memory Card specification version 1.0 • MCI operates at a rate of up to master clock divided by 2 • Supports PDC connection • Embedded power management to slow down clock when the bus is inactive • Supports up to sixteen slots (through multiplexing) • One slot for one MultiMediaCard Bus (up to 30 cards) or one SD Memory Card • Support for stream, block and multi-block data read and write
Multimedia Card Interface • MultiMediaCard Bus • The MultiMediaCard communication is based on a 7-pin interface (clock, command, one data and three power lines).
Multimedia Card Interface • SD Memory Card Bus • The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines).
USART • Features • Programmable Baud Rate Generator • Parity, Framing and Overrun Error Detection • Line Break Generation and Detection • Automatic Echo, Local Loopback and Remote Loopback Channel Modes • Multi-drop Mode: Address Detection and Generation • Interrupt Generation • 5, 6, 7, 8 and 9-bit Character Length • Protocol ISO7816 T=0 and T=1 • Modem, Handshaking (Hardware and Software) and RS485 Signals • Infrared Data Association (IrDA) 115.2 Kbps • Two Dedicated Peripheral Data Controller Channels
USART • Hardware Handshaking • ISO7816 Mode
USART • IrDA Mode • RS485 Mode
Serial Peripheral Interface • Features • Serial Interface between CPU and External Peripherals • Master or Slave Mode • Full duplex 3 wires synchronous transfer • MISO: Master In Slave Out • MOSI: Master Out Slave In • SPCK: SPI Clock • Maximum SPI baud rate clock: MCK/4 • 4 External Slave chip selects • 8 to 16-bit Programmable Data Length • Mode Fault Detection in Master Mode • 2 Dedicated PDC Channels
Two Wire Interface • Features • Master Mode • Compatible with Standard Two-wire Serial Memory • One, Two or Three Bytes for Slave Address • Sequential Read/write Operations
Two Wire Interface • Bus
System Timer • Features • One Period Interval Timer (PIT) • 16-bit programmable counter • periodic interrupt, useful for OS • One Watchdog Timer (WD) • 16-bit programmable counter • maximum watchdog period of 256s with a typical slow clock of 32.768kHz • One Real Time Timer (RTT) • 20-bit free-running counter • count elapsed seconds • 1s increment with a typical slow clock of 32.768kHz • count up to 1048576s (12 days) • Alarm to generate an interrupt
Timer/Counter • Features • Three 16-bit Timer/Counter channels • Wide range of functions: • Frequency measurement • Event counting • Interval measurement • Pulse generation • Delay timing • Pulse Width Modulation • Clock inputs • 3 External and 5 Internal • Two configurable Input/Ouput signals • Internal interrupt signal
Real Time Clock • Features • Low power consumption • Complete time of day clock • Programmable periodic interrupts • Alarm • Five programmable fields: Month, Date, Sec, Min and Hour • Y2K compliant • BCD Format
Ethernet MAC • Features • Compatible with IEEE Standard 802.3 • 10 and 100 Mbits per Second Data Throughput Capability • MII or RMII Interface to the Physical Layer • Register Interface to Address, Status and Control Registers • DMA Interface • Interrupt Generation to Signal Receive and Transmit Completion • 28-byte Transmit and 28-byte Receive FIFOs • Automatic Pad and CRC Generation on Transmitted Frames • Address Checking Logic to Recognize Four 48-bit Addresses • Supports Promiscuous Mode Where All Valid Frames are Copied to Memory • Supports Physical Layer Management through MDIO Interface
USB Overview • USB is a master/slave protocol • Host side is complex ( 3 standards: UHCI, OHCI, EHCI) • Device side is supposed to be easy • In the embedded world some hosts (mini-hosts) only support some kind of devices (ex. AT43xxx). • Class drivers is a part of the USB success story: most common devices can be plugged without specific drivers. • USB 2.0 specification supercedes USB 1.1 specification • USB 2.0 LS ( USB1.1 at 1.5Mbps) • USB 2.0 FS ( USB 1.1 at 12Mbps) • USB 2.0 HS (480 Mbps)
USB Host Port • AT91RM9200 embeds a full OHCI Host controller • All OHCI drivers can run on the AT91RM9200 • Very difficult to program in a standalone application • AT91RM9200 OHCI host controller integrates a root hub with 2 downstream ports. • Port transceiver are embedded in the AT91RM9200 • VBUS is provided by the PCB • Discrete components around the USB port are limited to few resistors, no external transceivers • AT91RM9200 OHCI host controller is one of the 4 ASB bus masters. • Internal FIFOS warranty the bus latency and the AT91RM9200 has no external master which can hold the bus for a long time • The 12Mbps can be reached
HID MS HUB Etc… USB Protocol Driver API Host Controller regs Host Controller Driver (HCD) OHCI-UHCI-EHCI USB Host Software Stacks • Linux and WIN CE provides • OHCI HCD driver • USBD Driver • Main class drivers: Hub, HID, Mass storage, Printer, … • Symbian and RTOS does not provides USB host stack driver • SW Ips provider are able to provide solutions for RTOS • Softconnex, Philog, … • It is still possible to build a mini host from our full host:
AT91RM9200 HC existing SW solutions • Linux solutions are available and integrated in the linux-2.4.21-rmk1 kernel • USB mouse or flash disk examples on the CDROM • WinCE solutions are existing but have not been tested/integrated by the AT91 SW application group • Refer to Adeset • Softconnex solutions (USBLink) are exhaustive and reliable • The stack is available with the Integrity demo • The AT91 SW application group validate the HC with UBSLink + Nucleus • Philog has developed a solution for one of the AT91RM9200 lead customer.
USB Device Port • When a new device is plugged to a host, the host enumerates the device and automatically looks for a device driver. (Plug and Play) • 2 needs => 2 philosophies • The device belongs to a standard class driver: HID. Mass storage. In this case, no needs from a custom driver on the host but device firmware is more difficult. • The device defines its own protocol. In this case, a custom driver must be developed on the host side (PC driver). This could be a very difficult task but the device firmware can be very easy. • There is no standard in terms of HW for the device. There is no existing standard solutions in Linux or WinCE.
AT91RM9200 USB Device Port • USB transceiver embedded: no need of external companion chip • USB 2.0 full speed compliant (12 Mbps) • A FIFO is associated with each endpoint • No DMA, packets can not be corrupted by the ASB bus latency • Two data banks per endpoint => ping-pong
AT91RM9200 USB Device Port • AT91RM9200 USB device configuration • EP0: 8 bytes control transfers • EP1, EP2: 64 bytes bulk + ISO + Interrrupt transfers • EP3: 8 bytes bulk + ISO + Interrrupt transfers • EP4, EP5: 256 bytes bulk + ISO + Interrrupt transfers
USB device examples • Mass Storage device • The device exports one part of its file system • The host OS (W2k, XP, Linux) will use its default mass storage driver and mount the new disk in its file system • The device will require: • A file system with the media driver (SDCard, MMC, …) • A mass storage driver (Philog, Softconnex, …) • Nothing is provided for free in the AT91 library • A negociation is in progress to have a demo from Softconnex… • USB bulk device • The device communicates with the host through 2 unidirectional pipes (bulk In and bulk out) • The host OS will search for a custom driver. • The device will require: • A simple application build from the AT91 library samples
Serial Synchronous Controller • Features • 1 to 32-bit Programmable Data Length • Receiver and Transmitter Parts Able to Operate Synchronously or Independently, Each Part Interfacing with a Data Signal, a Clock Signal and a Frame Synchronization Signal • Provides Communication with External Devices in Master or Slave Mode: • CODECs in Master or Slave Modes • DAC through Dedicated Serial Interface, Particularly the I2S • Time Division Multiplexed Buses • Magnetic Card Reader • Printer and Scanner Interface • SPI Used in Full or Half Duplex, in Master or Slave Modes with One Chip Select Only
Serial Synchronous Controller • Audio Application
Serial Synchronous Controller • Codec Application
Serial Synchronous Controller • Time Slot Application
