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Reconfigurable Embedded Processor Peripherals

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luthando
11 diapositives · 175 Views · Mar 03, 2013

Explore how Partial Reconfiguration enables FPGA modules to swap functions on-the-fly, enhancing processor functionality in Xilinx devices for aerospace and defense applications. Learn about challenges, methodologies, and benefits of using Partial Reconfiguration. Discover key terms, example designs, and design considerations for PR peripherals.

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Reconfigurable Embedded Processor Peripherals
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  1. Reconfigurable Embedded Processor Peripherals Xilinx Aerospace and Defense Applications Brendan Bridgford Brandon Blodget

  2. Background • Partial Reconfiguration (PR) allows FPGA design modules to be swapped on-the-fly • Design modules with different functions time-share the device resources • Partial bitstreams for each module are stored in non-volatile memory outside of the FPGA • The FPGA can load the partial bitstreams and partially re-configure itself while the base design operates uninterrupted

  3. PR for Embedded Processors • Partial Reconfiguration allows for vastly expanded processor functionality • Specialized processing units can be added/removed during operation, without losing state. • Allows processor peripherals to share resources: • Multiple Crypto Algorithms • Multiple Communication Waveforms • Multiple DSP/Arithmetic functions • Result: reduced device count, smaller FPGAs

  4. PRM_B PRM_A Partial Reconfiguration Terms and Acronyms • PR: Partial Reconfiguration (method) • Programming a subset of the configuration memory (usually via SelectMAP or ICAP) XC2VP30 • PR Region • A region set aside for PRMs Base Design • PRM: Partial Reconfig Module • A module that can time-share a PR region • Base Design • All non-PRM design elements

  5. PRM 3DES core PRM DES core Example Design • A reference design has been built to illustrate PR • Features: • PPC405 processor (base) • UART interface (base) • ICAP (base) • SystemACE CF controller (base) • Reconfigurable 3DES/DES encryption cores (Partially Reconfigurable Modules) XC2VP30 OPB UART PPC 405 ICAP ACE CTLR

  6. PRM 3DES core PRM DES core Why Use PR? • Partial Reconfiguration allows you to use fewer, smaller devices. • For example, can’t fit both a 3DES and a DES core into the same XC2VP30. • Benefit of PR increases with the more PRMs. XC2VP30 OPB UART PPC 405 ICAP ACE CTLR

  7. PR Challenges forEmbedded Processors • Normal processor architectures are static, so all register addresses are pre-assigned and fixed • This isn’t so for a processor with PR peripherals. How do we: • Build drivers? • Write code that works for all possible processor combinations? • Allocate memory? • Know what the processor consists of at any given time?

  8. PR Peripheral Design – Software • Reserve enough memory space to accommodate the needs of the largest PR module. • Use the same driver for all PR modules. • All PR modules must have the same base address, address range, and register addresses • Detect the current PR module through hardware ID checking or with a variable.

  9. PR Peripheral Design - Hardware • Define enough registers to accommodate PR peripheral with the greatest number of I/O • Top level HDL description will be the same for all peripherals • All peripherals will have the same top level entity name, ports. • Differences between PR peripherals will appear in lower-level modules.

  10. Logical to Physical Memory Mapping • EDK produces a .bmm file to establish the mapping between logical and physical memory • The same .bmm file can be used for all versions of the design, since physical memory is in the base design.

  11. Conclusions • Embedded PR systems can squeeze more functionality into less silicon • Software design is similar to other embedded systems • Xilinx Application Note XAPP290 describes the Partial Reconfiguration Hardware Design Flow