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IceCube DOMMB Firmware

The Fall 2003 collaboration meeting focused on the firmware development of the IceCube DOMMB and DOMAPP. Thorsten Stezelberger presented updates on the CPLD and FPGA designs, highlighting that the CPLD design is nearly complete with minor changes required for mainboard Rev. 3. The status of the DOMAPP component showed that data acquisition is 80% complete, while calibration and local coincidence functionalities are still in progress. The expected completion time for the DOMAPP firmware is approximately 4 weeks, with communication handled by Kalle.

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IceCube DOMMB Firmware

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  1. IceCube DOMMB Firmware Collaboration Meeting Fall 2003 Mons Mons Thorsten Stezelberger

  2. DOMMB Block Diagram Mons Thorsten Stezelberger

  3. Programmable Logic • CPLD (lowest level programmable logic device needed) Almost finished. Minor changes needed for mainboard Rev 3 and to make the design more robust. • FPGA Under development (see the following slides) Mons Thorsten Stezelberger

  4. Required FPGA Designs • STF 99% Done for testing • ConfigBoot Preliminary Versionminimal boot • IceBoot Preliminary Versionnormal boot • DOMAPP ~50% Done for data taking For software development purposes the SFT FPGA can be used for the ConfigBoot and the IceBoot FPGAs Mons Thorsten Stezelberger

  5. DOMAPP Block Diagram Mons Thorsten Stezelberger

  6. DOMAPP Status • Data Acquisition ~80% Done • Calibration Sources 0% Done • Local Coincidence 0% Done • Communication Provided by Kalle • Compression 0% Done Estimated time to finish DOMAPP firmware: ~4 weeks Mons Thorsten Stezelberger

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