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Input/Output Organization (Chapter 4)

Input/Output Organization (Chapter 4). http://www.pds.ewi.tudelft.nl/~iosup/Courses/2011_ti1400_8.ppt. The “Data Deluge”: Trivia. The Petabyte Age: Because More Isn't Just More — More Is Different, Wired, 23 June 2008. http://www.wired.com/science/discoveries/magazine/16-07/pb_intro#.

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Input/Output Organization (Chapter 4)

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  1. Input/Output Organization(Chapter 4) http://www.pds.ewi.tudelft.nl/~iosup/Courses/2011_ti1400_8.ppt

  2. The “Data Deluge”: Trivia The Petabyte Age: Because More Isn't Just More — More Is Different, Wired, 23 June 2008. http://www.wired.com/science/discoveries/magazine/16-07/pb_intro#

  3. The “Data Deluge”: Facts and Predictions "Everywhere you look, the quantity of information in the world is soaring. According to one estimate, mankind created 150 exabytes (billion gigabytes) of data in 2005. This year, it will create 1,200 exabytes. Merely keeping up with this flood, and storing the bits that might be useful, is difficult enough. Analysing it, to spot patterns and extract useful information, is harder still.“The Data Deluge, The Economist, 25 February 2010.

  4. “Data Deluge”: The Mobile Example exabyte Battling a Wireless Deluge: AT&T, Other Carriers Use Wi-Fi 'Hotzones' to Siphon Off Smartphone Traffic, Tech Journal, 2 February 2011. Read more: http://online.wsj.com/article/SB10001424052748704124504576118353354099780.html#ixzz1LEpF4TuA

  5. “Data Deluge”: The Personal Memex Example • Vannevar Bush in the 1940s: record your life • MIT Media Laboratory: The Human Speechome Project/TotalRecall, data mining/analysis/visio • Deb Roy and Rupal Patel “record practically every waking moment of their son’s first three years”(20% privacy time…Is this even legal?! Should it be?!) • 11x1MP/14fps cameras, 14x16b-48KHz mics, 4.4TB RAID + tapes, 10 computers; 200k hours audio-video • Data size: 200GB/day, 1.5PB total

  6. “Data Deluge”: The Gaming Analytics Example • EQ II: 20TB/year all logs • Halo3: 1.4PB served statistics on player logs

  7. “Data Deluge”: Datasets in Comp.Sci. The FailureTraceArchive Dataset Size http://gwa.ewi.tudelft.nl 1TB/yr 1TB GamTA http://fta.inria.fr 100GB P2PTA 10GB 1GB Year ‘06 ‘09 ‘10 ‘11 Peer-to-Peer Trace Archive … PWA, ITA, CRAWDAD, … • 1,000s of scientists: From theory to practice 7

  8. The Simplest(?) Problem: How to Access Data by the CPU/Cores? • Computers must be able to communicate with outside • Large varietyof devices • size • speed • distance • Timing and electricalproperties not the same as within CPU

  9. Single-bus structure Processor Memory Bus I/O device #1 ............ I/O device #n

  10. Multiple buses Memory memorybus Processor I/O Bus ............ I/O device #n I/O device #1

  11. Buses and interfaces Bus contains generally three bit strings: • Data linesto transport data • Address linesto identify devices • Control linesthat take care of correct transfer of data

  12. Interfaces Devices are coupled to bus through interface: • Address decoder • for detection if data is for device • Data registers • to store incoming and outgoing data • Status and controlregisters • to certify status of device • to control transfer

  13. Interface organization Address lines Data lines Control lines I/O interface Address Decoder Data and Status registers Control circuits Device

  14. Video terminal CPU DATAIN DATAOUT SOUT SIN Keyboard Display Video terminal

  15. Operation (1) Busy waiting: READWAIT Branch to READWAIT if SIN=0 Input from DATAIN to R1 WRITEWAIT Branch to WRITEWAIT if SOUT=0 Output from R1 to DATAOUT Move DATAIN, R1 Move R1, DATAOUT I/O-instructions:

  16. Operation (2) 2 1 0 IOSTATUS SIN SOUT DATAIN DATAOUT READWAIT Testbit #1, IOSTATUS Branch=0 READWAIT Move DATAIN, R1

  17. I/O Instructions • Memory-mapped I/O • the registers of the devices have addresses in the same space as main memory locations • normal instructions can be used • move DATAIN, R1 • I/O instructions • special instructions for I/O • IN device, data • OUT data, device

  18. IOPROC1 IOPROC2 Memory and register structure Memory CPU ......

  19. Address spaces memory mapped separate address spaces 0 0 CPU CPU 1 1 2 2 0 0 IOPROC1 1 IOPROC1 1 2 2 0 3 IOPROC2 1 IOPROC2 4 2 5 0 6 Mem Mem ...... ......

  20. I/O and Programming There are two basic mechanisms for I/O: • Programmed I/O • Non-programmed I/O

  21. Programmed I/O • By executing of special program in CPU • Unconditional I/O • no synchronizationwith I/O device • Passive signaling • synchronization between CPU and Device by programmed interrogation by CPU • Active signaling • synchronization between CPU and Device by active interrupt of Device

  22. Non-programmed I/O I/O is done by separate active entity • Direct Memory Access(DMA) • some intelligence in device takes care of data transport • Special I/O processors

  23. Interrupts Compute routine Print routine 1 jump ... Interrupt i i +1 ..... ..... .... return M

  24. Service Routines • I/O device alerts CPU by hardware signal called interrupt signal • Usually special line in control group of I/O bus is used for this: interrupt request line • CPU stops program and starts executing service routine • Much like executing subroutine • Except: these routines have nothing in common !!

  25. Handling interrupts • Device raises interruptrequest • Processor interrupts program in execution • Interrupts are disabled • Device is informed of acceptance and, as a consequence, lowers interrupt • Interrupt is handled by service routine • Interrupts are enabled • Execution of interrupted program is resumed

  26. Multiple devices • How can processors distinguish devices ? • How can processors obtain the appropriate starting addressservice routine ? • Should we allow a new interruptwhile another is being served ? • How do we handle simultaneous interrupts ?

  27. Interrupt line INTR = INT1 + INT2 + .... + INTn interrupt request CPU INT1 INT2 INTn Finding device by POLLING : - search for device with IRQ bit set in status register

  28. Vectored Interrupt • Device sends identification codeon bus • Called interrupts vector • Issued after GRANT signal from CPU interrupt request CPU INT1 INT2 INTn grant

  29. Interrupt priority priority circuit CPU INT1 INT2 INTn grant1 grant2 grant3

  30. Bus arbitration (1) bus release line (rel_i) interrupt request line (req_i) CPU grant bus is free iff: (rel_1 • rel_2 • ..... • rel_n) =1

  31. Bus arbitration (2) • Request: set req_i to 1 • Acquire: if grant=1, then set req_i to 0(interrupt once)and set rel_i to 0 (prevent others from interrupting) • Release: set rel_i to 1 grant = (req_1 + req_2 + ..... +req_n) • (rel_1 • rel_2 • ..... • rel_n) at least one request bus released by all

  32. PowerPC interrupt structure (1) MSR = Machine State Register 0 16 17 21 25 31 EE SE EP PR EE = External interrupt enable PR = Privilege level SE = Single step trace exception enable EP = Exception prefix EP=0  address service starts at 000001F4 EP=1  address service starts at FFF001F4

  33. PowerPC interrupt structure (2) • PowerPC has two special Save/Store registers: SRR0 and SRR1 • After interrupt: MSR PC SRR0 SRR1 Clear interrupt enable bit in MSR

  34. IA-32 interrupt structure (1) Processor status register (EFLAGS) • CF, ZF, SF, OF: condition code flags • TF: trap flag • IF: Interrupt Enable Flag • IOPL: I/O Privilege Level (4 levels) • IA-32 has two interrupt request lines 31 13 12 11 9 8 7 6 0 IOPL OF IF TF SF ZF CF

  35. IA-32 interrupt structure (2) • Steps when an interrupt occurs: • push processor status register, current segment register (CS), and instruction pointer (EIP) onto the stack • clear interrupt-enable flag if needed • fetch starting address of interrupt-service routine from Interrupt Descriptor Table and load it into EIP • At end of routine, execute IRET

  36. Example DATAIN 6 2 1 0 STATUS IE SIN SOUT interrupt keyboard interface

  37. Memory Layout STATUS DATAIN 32 K I/O space ..... LINE ..... ..... buffer area 32 K program space 1F4 address READ READ .....

  38. PowerPC: Initialization INTVEC EQU $1F4Interrupt vector address (location where start address of interrupt routine is stored) INTEN EQU $40Keyboardinterrupt enable INTDIS EQU 0anddisablemasks (will bestored in status registerof device) NEWMSR EQU $8000Desired contents of MSR (external interrupt enable) RTRN EQU $0DCode Carriage Return (forchecking end-of-line)

  39. PowerPC: Interrupt Processing (1) START ADDI R2,0,READGet address of service STW R2,INTVEC(0)routine and store at interrupt vector location ADDI R2,0,LINEGet address of LINE STW R2, PNTR(0)and store at PNTR ADDI R2,0,INTENStoreinterrupt enable STW R2,STATUS(0)in STATUS register

  40. PowerPC: Interrupt Processing (3) ADDI R2,0,NEWMSRStorenew MSR MTSRR1 R2in SRR1 ADDI R2,0,MAINStorenew PC MTSRR0 R2in SRR0 RFIReturn From Interrupt (use new MSR and PC)

  41. PowerPC: Program (1) MAIN <main program> ..... READ .....Save registers LBZ R30,DATAIN(0)Get input character LWZ R31,PNTR(0)Load value at PNTR STBU R30,1(R31)Store character in buffer STW R31,PNTR(0) Update PNTR for next character PNTR

  42. PowerPC: Program (2) CMPWI CR1,R30,RTRNCheck for CR(end of BNE CR1,DONEline) ADDI R2,0,INTDISStore interrupt disable STW R2,STATUS(0)in STATUS register BL TEXTCall subroutine for dealing with line DONE ....Restore saved registers RFIReturn from interrupt EOL next character

  43. IA-32: Program (1) MAIN:MOV EOL,0not yet end of line MOV BL,4set keyboard OR CONTROL,BLinterrupt enable STIset interrupt flagin processor register READ:PUSH EAXsave registers PUSH EBX MOV EAX,PNTRload address pntr MOV BL,DATAINget input, MOV [EAX],BLstore it, INC DWORD PTR [EAX]and increment pntr

  44. IA-32: Program (2) CMP BL,0DH char=end of line? JNE RTRNno MOV BL,4 yes XOR CONTROL,BL so disable interrupts MOV EOL,1 and set EOL flag RTRN:POP EBXrestore registers POP EAX IRETreturn from interrupt

  45. Other interrupts • Not only I/O devices can cause interrupts • Recovery from errors, e.g.: • illegal OP code used • division by 0 • Debugging • Privilege exception

  46. Operating Systems (1) • In general, interrupts controlled by Operating System • CPU can be in user mode or supervisormode • Privileged instructions only allowed in supervisor mode • starting of I/O operations • setting of priorities • setting of clock values

  47. Operating Systems (2) • Process: program in execution • Program • Data • Status: PC, Registers, etc • State of a process: • Running • Runnable (waiting for CPU) • Blocked (waiting for something else) • Multi-tasking • Multiple tasks in execution • Time-slicing • Divide time across processes

  48. Operating Systems (3) • Context switch: change of processes • After clock interrupt: dispatcher chooses suitable process • Device drivers: service routines for devices • System Call: call to OS service routine • printf (“%d\n”,a) • fscanf (file,”%d\n”,&a)

  49. OS init, services, scheduler OSINIT Set interrupt vectors Time slice clock <- SCHEDULER Trap <- OSSERVICES VDT interrupts <- IODATA ... OSSERVICES Examine stack to determine request Call appropriate routine SCHEDULER Save current context Select runnable process Restore saved context of new process Return from interrupt Set addresses for dealing with these interrupts Context switch

  50. I/O routines IOINIT Set process status to blocked Initialize memory buffers Call device driver to initialize device (e.g., VDT) Return from subroutine IODATA Poll devices to determine source of interrupt (e.g., VDT) Call appropriate driver if END=1 then set process to runnable Return from interrupt

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