IEEE 1364 Standardization of SystemVerilog 3.1a

1. IEEE 1364 Standardization of SystemVerilog 3.1a Michael McNamara, 1364 Chair Peter Ashenden, DASC Chair presented 5-20-2004

2. Verilog for the 21st Century • Extend the very successful base language with constructs facilitating easier and more robust specification of larger circuit designs that address the needs of the multi company DV teams and DV flows presented 5-20-2004

3. Goal and Objective • Integrate the work of the Accellera SystemVerilog committees into the base IEEE 1364 specification • Make the work available quickly • Work to facilitate widespread adoption presented 5-20-2004

4. Today’s Situation • SystemVerilog 3.1a Extensions to IEEE 1364-2001 (SV) is an approved and available Accellera specification • IEEE-1364 has an authorized project to add SystemVerilog-like features to the language • Some at Accellera apparently fear IEEE-1364 will make unnecessary changes or introduce unreasonable delays when integrating SV into 1364 presented 5-20-2004

5. How Did We Get Here? • Bold experiment by Accellera to quickly develop language enhancements outside of what was perceived as a cumbersome IEEE process. • Initial partnership with IEEE-1364 who opened PAR in order to incorporate results of experiment. • Overtime, trust between organizations waned • Miscalculation – experiment took three years to result in a standard that Accellera felt was ready for transfer. • Additional donations & expanded scope • Conflict with Accellera’s Property Specification Language effort • Unreasonable expectation – IEEE-1364 expected the process would be quicker, or could be pipelined • Transfer 3.0 while working on 3.1 • Transfer 3.1 while working on 3.1a presented 5-20-2004

6. Available Options • Accellera passed motion in 2003 to transfer SV to the IEEE by June of 2004 • Could transfer SV to new PAR via IEEE-CAG • Issues of overlap need to be addressed • Issues of synchronization need to be addressed • Could transfer SV to existing PAR under IEEE-DASC • Understanding & mutual agreement of integration plan with existing work needs to be achieved presented 5-20-2004

7. Transfer SV to 1364: What would happen? • IEEE 1364 adopted formal Extension Guidelines during its spring meetings; these govern all extensions processed through the BTF • IEEE 1364 considered and formulated a response to Accellera’s request for process on how the IEEE 1364 would incorporate SV into 1364 at the 17 May 2004 IEEE 1364 meeting presented 5-20-2004

8. IEEE 1364 Response • The 1364 WG authorized its Chair to present a menu of choices to Accellera, which are: • Trial Use Standard & Ballot • Preliminary Draft • Trial Use & Preliminary Draft • Merged Document & Full Ballot presented 5-20-2004

9. 1: Trial Use Standard • The IEEE 1364 Working Group would create an 1364.n Trial Use Standard based solely upon the SystemVerilog 3.1a extension document, and begin balloting this right away • Based on experience of members of the committee, it requires six months to complete the IEEE balloting process and obtain an official IEEE Trial Use Standard status • Release date: January 2005 • Trial Use standards are good for two years presented 5-20-2004

10. 2: Preliminary Draft • The IEEE-1364 Working Group would immediately combine SystemVerilog into the current IEEE-1364 draft, with only minimal review of fit and finish • 1364 would make that draft available to the world as an official draft release of the Working Group • Estimate is this would require six months • Release date: January 2005 • Work would continue to refine fit and finish, and incorporate other 1364 donations • Final standard would be released in June of 2006 presented 5-20-2004

11. 3: Trial Use & Preliminary Draft • The IEEE 1364 Working Group would prepare a Trail Use Standard and manage it through ballot, while simultaneously merging the contents of SV into 1364 and prepare a public draft • Release date for both: January 2005 • Work would continue to refine fit and finish, and incorporate other 1364 donations • Final standard would be released in June 2006 presented 5-20-2004

12. 4: Complete Standard • The IEEE 1364 Working Group would begin work to merge current 1364 draft with SV and take that to ballot as a full standard. • Estimate is the work would take one year, plus six months to ballot • Release date: January 2006 • Simultaneously IEEE-1364 would open a sub-par to support further concurrent development of the standard targeted for a later release date. presented 5-20-2004

13. General Considerations • The IEEE 1364 group for any of these efforts may form subsidiary “dot" pars coordinated under 1364, to facilitate faster parallel standardization and more logical document layout • For example combining all PLI from SystemVerilog & IEEE-1364 into a single document, with a number like 1364.2; Assertions into 1364.3; Testbench into 1364.4, et cetera • IEEE 1364 will hire Program Manager to drive process • Funding sources are identified, and more are welcome presented 5-20-2004

14. Timelines Option 1 & 2 in parallel presented 5-20-2004

15. Finally • Should Accellera decided to proceed with a separate PAR through CAG, the 1364 WG petitions Accellera to also donate SystemVerilog 3.1a to this WG for the eventual long term merging of all of the extensions into the base 1364 work presented 5-20-2004