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Today’s class

Today’s class. Microarchitecture. The part of the CPU containing the ALU, its inputs, and its outputs This is an example data path for the IJVM microarchitecture developed in your text. Data Path. 6 control lines F 0 and F 1 determine ALU operation ENA and ENB for enabling the inputs

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Today’s class

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  1. Today’s class • Microarchitecture Computer Architecture I - Class 9

  2. The part of the CPU containing the ALU, its inputs, and its outputs This is an example data path for the IJVM microarchitecture developed in your text Data Path Computer Architecture I - Class 9

  3. 6 control lines F0 and F1 determine ALU operation ENA and ENB for enabling the inputs INVA for inverting the left input INC for forcing a carry into the low-order bit, effectively adding 1 to the result ALU Signals and Functions Computer Architecture I - Class 9

  4. Data Path Timing Computer Architecture I - Class 9

  5. Memory • Example machine has two different ways to communicate with memory • 32-bit word-addressable memory port • Controlled by two registers • MAR (Memory Address Register) • MDR (Memory Data Register) • 8-bit byte-addressable memory port • Controlled by one register • PC, which reads 1 byte into the low-order 8 bits of MBR Computer Architecture I - Class 9

  6. Memory Operation Computer Architecture I - Class 9

  7. Microinstruction Format Computer Architecture I - Class 9

  8. Sequencer • Which control signals should be enabled on each cycle? • Determined by the sequencer • Must produce two kinds of information each cycle: • The state of every control signal in the system • The address of the microinstruction that is to be executed next Computer Architecture I - Class 9

  9. Computer Architecture I - Class 9

  10. Stacks for Local Variable Storage • Procedures need somewhere to store local variables that won’t be interfered with by recursive calls Computer Architecture I - Class 9

  11. Stacks for Operand Storage • Need someplace to hold operands during an arithmetic operation Computer Architecture I - Class 9

  12. The IJVM Memory Model Computer Architecture I - Class 9

  13. The IJVM Instruction Set Computer Architecture I - Class 9

  14. Calling a Procedure • Push onto the stack a reference (pointer) to the object to be called (since our architecture is not object-oriented, this will not be used but is retained for consistency) • Push the procedure’s parameters onto the stack • Execute INVOKEVIRTUAL instruction Computer Architecture I - Class 9

  15. The Stack and INVOKEVIRTUAL Computer Architecture I - Class 9

  16. The Stack and IRETURN Computer Architecture I - Class 9

  17. Compiling Java to IJVM Computer Architecture I - Class 9

  18. Microprogram for the Mic-1 Computer Architecture I - Class 9

  19. In-Class Exercise • Give two different IJVM translations for the Java statement i=k+n+5; (refer to the instruction set on page 250 of your text) • How long does a 2.5 GHz Mic-1 take to execute the Java statement i=j+k;? Give your answer in nanoseconds. (Refer to the code on page 254 of your text, and to the microprogram code on page 262) Computer Architecture I - Class 9

  20. Increasing Speed of Execution • Reduce the number of clock cycles needed to execute an instruction • Simplify the organization so that the clock cycle can be shorter • Overlap the execution of instructions Computer Architecture I - Class 9

  21. Merging the Interpreter Loop with the Microcode Computer Architecture I - Class 9

  22. A Three Bus Architecture Computer Architecture I - Class 9

  23. An Instruction Fetch Unit • The ALU is used nearly every cycle for a variety of operations having to do with fetching the instruction and assembling the fields within the instruction, in addition to the real “work” of the instruction • Need to free the ALU from some of these tasks • Create an independent unit to fetch and process the instructions Computer Architecture I - Class 9

  24. The Mic-2 Datapath Computer Architecture I - Class 9

  25. Microprogram for the Mic-2 Computer Architecture I - Class 9

  26. In-Class Exercise • Reconsider the Java statement i=j+k; • How long does it take to execute this statement on a 2.5 GHz Mic-2? (refer to the microprogram for the Mic-2 on page 282 of your text) Computer Architecture I - Class 9

  27. 3 cycles to operate: Load A and B Perform the operation and load C Write the results back to the registers Each of these pieces is called a microstep Pipelining –The Mic-3 Computer Architecture I - Class 9

  28. The Mic-2 Code for SWAP Computer Architecture I - Class 9

  29. The Implementation of SWAP on the Mic-3 Computer Architecture I - Class 9

  30. Pipeline Computer Architecture I - Class 9

  31. Cache Memory A system with three levels of cache. Computer Architecture I - Class 9

  32. Cache Model • Main memory is divided up into fixed-size blocks called cache lines • A cache line consists of 4 to 64 consecutive bytes • Lines are numbered consecutively starting at 0 Computer Architecture I - Class 9

  33. Direct-Mapped Caches Computer Architecture I - Class 9

  34. Set-Associative Caches Computer Architecture I - Class 9

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