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TSF Simulation

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  1. TSF Simulation L1 simulation review Aug 2005 Jamie Boyd

  2. Outline • Algorithm overview • Hardware overview • Simulation software overview • Configuration • Validation • Methods • Plots

  3. TSF Algorithm overview Pivot wire unique to pivot cell. Every other wire shared by other pivot cells Pivot wire • TSF finds track segments in 8-wire pivot groups (10 pivot groups in radial direction/SL , 96-256 in phi for each SL, => 1776 for full DCH) • Every wire in the pivot group represented by a 2bit counter – counts how many clk 4 ticks since wire was last hit • Every clk4 all 8x2bit counters used to look up segment from pre-calibrated LUT (0xffff possible addresses). Look-Up returns information on segment quality (2 bit weight) , segment phi value (5/6 bit) , dphi (4/3 bit) , and time info (5 bit) • Best segment in 3 clk ticks chosen and stretched / formatted for output to BLT / ZPD or BLT / PTD • TSF receives binary info from all DCH wires every clk4 • Produced segments have phi resolution ~800um and a time resolution <70ns

  4. Engines ZPD clk 4 DCH data clk 4 clk 4 Output Formatter Input Formatter clk 8 PTD clk 8 Hardware overview • Had to replace all TSFs for upgrade but algorithm essentially unchanged • Better phi resolution (6 bits for phi rather than 5) • Ship segments for Stereo & Axial Superlayers (previously Axial only) • Format segments for ZPD • Used opportunity to simplify hardware design a lot (24 FPGAs / board -> 5!) LUT data on configure DAQ Data used by L3 clk 4 Look-Up Best segment choosing Stretching done here

  5. HepAList<DchDigi> L1DTsfHitMaker L1SimTimeBuffer<L1SimStreamVector<L1DTsfHit> > L1DTsfSimModule L1SimTimeBuffer<L1SimStreamVector<L1DTsfSimDigi> > L1DTsfStretcher L1DTsfPPMakeDigis L1SimTimeBuffer<L1SimStreamVector<L1DTsfSimDigi> > Simulation Code overview 2 possible algorithms for dealing with 2 hits within 3clk4s of each other on same wire. trgDC not same as hardware here. For now copy trgDC as real algorithm has problem with background overlay. Looking into this. • HitMaker takes DCH digis quantizes into clk4. • Output is a L1DTsfHit timebuffer (contains Dch digi and how many clk4 ticks ago the hit was wrt time buffer tick) FcsClock • SimModule simulates the Look-Up and choosing best segment in 3clk 4 ticks. Output is clk4 timebuffer LUT • Stretcher stretches the segment in time. Output is clk8 timebuffer LUT DAQ Latency HepAList<L1DTsfDigi> Most modules also need Geometry

  6. Configuration issues • TSF configuration data • LUT (big~2.5M) • DAQ latency (1 short) • Both used in hardware and simulation • In both cases retrieved from config DB in same way with config key of run / job • DAQ latency defines where output digis are in time wrt digi timing window (8 clk4 ticks) • Was not configurable in trgDC

  7. LUT and entries • Because of the change in phi resolution need to be careful with the look-up entry • Interpretation of the bits different • Conversion from hardware phi to physical phi different • LUT complicated as needs to be • Used in online to load into board (xtc representation) • Used in offline (sim) / L3 here want to be able to seamlessly use without knowing if its new (6bit) or old (5bit) LUT • Set up abstract class L1DTsfLutEntry with concrete instantiations L1DTsf5/6BitLutEntry • The LUT is a big (0xffff x 10) array of these entries • It is set up during job configuration the LUT associated with the config key is loaded from the config DB and stored in the event. • The user doesn’t know (or care) if this is 5/6 bit Lut and can ask LutArray->getEntry(sl,address)->phi() in either case getting sensible results • Not quite true as hardware phi value is also available – interpretation of this depends on knowing which LUT you are using • But true in simulation and in L3

  8. Validation • TSF boards validated by running (new) simulated data from input memory and comparing ZPD output in output memory • Tested on 6K BB evts / 1K bhabha / 2K Kspi0 / 2K pi0pi0 / 2K Ks nunu / 1K tau tau – no errors (this used different HitMaker than used now with current hit maker get discrepancy at 0.001% level) • This does not test input data path, DAQ data or BLT output • Input data path different between simulation and data anyway (we use DchDigi not same as TIOM data) • (During this process fixed some small bugs in simulation and some bugs in firmware) • Boards also validated against old TSF boards (parasitic commissioning) validates DAQ data of boards • New simulation basically agrees with trgDC (low level differences) • Plots on next few pages uses DAQ data from boards / new simulation & trgDC

  9. Validation plots – BhaBha MC

  10. Validation plots – BB MC (run4)

  11. Validation plots – BB MC (run5)

  12. TSF resolution Missing background Looks good

  13. Conclusions • New TSF simulation is working well • Simulation compared with hardware with no problems • Simulated distributions agree with both trgDC and data • Configuration done in better way to trgDC • One small issue with background overlay means hit maker algorithm not exactly same as hardware – being looked into – but current way is same as trgDC and is only 0.001% effect

  14. Some other changes • Now have 3 bit tick (before 2 bit – 1 bit lost in firmware) simulation can cope with either (as for data) • For trgDC no time cut put on TSF digis sent to L3 now time window applied as in data • HitMaker algorithm slightly wrong in trgDC (for hit on same wire within 3clk4s) we are trying to make the new simulation work with the correct algorithm – (but very small effect 0.001%)

  15. The Look-UP Taken from: L1DctConfig/L1DTsf5BitLutEntry.hh L1DctConfig/L1DTsf6BitLutEntry.hh • 5 bit • // LUT content: • // xxxx xxxx xxxx xxxx • // weight: 1100 0000 0000 0000 • // phi: 0011 1110 0000 0000 • // phiError: 0000 0001 1110 0000 • // delay: 0000 0000 0001 1100 • // stretch: 0000 0000 0000 0011 • 6 bit • // LUT content (of 16 bit LUT word): • // xxxx xxxx xxxx xxxx • // weight: 1100 0000 0000 0000 • // phi: 0011 1111 0000 0000 • // phiError: 0000 0000 1110 0000 • // delay: 0000 0000 0001 1100 • // stretch: 0000 0000 0000 0011 • // we also have the first 6 bits of the next 16 bits which is the • // rank • // xxxx xxxx xxxx xxxx • // rank: 0000 0000 0011 1111 • // not used: .... .... ..

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