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Development of Calorimeter Trigger System for sBelle at Hanyang University

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chipo
18 diapositives · 311 Views · Aug 21, 2014

This presentation outlines the design and implementation of the calorimeter trigger system for the sBelle experiment, focusing on advancements made by Byung-Gu Cheon and his team at Hanyang University. Key features include the integration of FAM and TMM modules for simplified and flexible trigger design, optimized signal handling for CsI(Tl) and pure-CsI detectors, and efficient monitoring schemes. The system aims to enhance data acquisition capabilities while minimizing cable usage through optical fibers, ultimately improving the overall functionality and performance of the sBelle detector system.

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  1. Calorimeter Trigger for sBelle ByungGu Cheon (Hanyang Univ) Super Belle Meeting, July 3-4, KEK

  2. 52 TKO crates Keep TKO systemorUse VME system

  3.  Official scheme I. Nakamura

  4. Belle ECL Electronics

  5. sBelle ECL trigger electronics SEQ PD+ Preamp GDL Shaper Final trigger (23) analog sum (12) Gb serial link (52) FAM ( FADC+ FPGA) Gb serial link (52) TMM ( FPGAs) Monitor

  6. Advantage of FAM + TMM scheme • Electronics chain will be very simple. • More flexible trigger design (because we have waveform information). • Reduction of cable; lots of bulky copper cables  52 optical fibers • Simple monitoring scheme (extra QT & TDCs are not necessary) • Easy handling of CsI(Tl) and pure-CsI together

  7. Flash ADC Module(FAM) • Input : 12 TC(4x4Xtlas) analog sum signals from Shapers • Continuous Input signal digitization @ 100MS/s 10~12bit • Find a pulse peak value or a partial sum of rising signal region • Digital discrimination of pulse height (programmable) • Output : 12 TC pulse height (or partial sum) + discriminator bit via Gbit link (with 10ns timing resolution) • TC output gain variation adjustment using look-up-table • One board(12 TC channels) / VME crate • Xtal gain adjustment should(may?) be done at Shaper.

  8. How FAM works

  9. Trigger & Monitoring Module(TMM) • Input : 52 x 12 TC signals from FAM modules • 7 FPGAs + VME interface • If all parts are not fitted into one board, partitioning & cascading design will be taken into account. • Output : 23 ECL final trigger signals 4 ECL trigger timings ( Final, Fwd, Barrel, Bwd ) 3 Total Energy ( >0.5, 1.0, 3.0 GeV) 4 Isolated Cluster Number ( 3 bits + 1 carry-bit) 11 types of Bhabha triggers 1 Cosmic Veto ** Any more useful trigger algorithm will be studied.

  10. Timing Latency • Peaking time=700ns @ peak position of analog sum signal • ADC pipeline latency @ FAM = ~100ns • Peak finding process @FAM = 100 ~ 200ns • Programmable delay @ FAM = ~300ns • Gbit transfer(~200bit) = ~200ns • Optical cable length(40~60m) = 200 ~ 300ns • 52 Trigger input alignment @ TMM = ~100ns • Trigger decision @ TMM = 100 ~ 200ns • ------------------------------------------------- • Total latency = 1800 ~ 2100ns

  11. FAM key algorithm test

  12. New EBM M.J.Lee

  13. Bhabha, Etot Calibration M.J.Lee

  14. Bhabha, Etot Timing M.J.Lee

  15. How can we handle pure CsI signals together with CsI(Tl) if we replace endcap Xtals ? • Peaking time and pulse height difference btw CsI(Tl) and pure CsI • All the triggers will be problematic without any correciton. • Timing and pulse height correction of pure CsI can be done @ TMM. • New FAM+TMM chain will generate all the trigger signals we provide now.

  16. Manpower • Hanyang Univ. : Y. Unno, S.H.Kim, I.S, Lee, B.G. Cheon (4) • Seoul N. Univ. : M.J. Lee, S. Ryu, S.K. Kim (3) • BINP : Y. Usov (1) • Notice co. : S.Y. Kim (1)

  17. Summary • FAM core firmware algorithm will be studied using new EBM. • We will start designing FAM if VME type Shaper design is ready. • Trigger algorithm will be studied with sBelle trigger simulator. • We have investigated the possibility of producing Shaper in Korea.

  18. Backup Slides