Electronic Engineering Final Year Project 2008 By Claire Mc Kenna

1. Electronic Engineering Final Year Project 2008By Claire Mc Kenna Title: Point of Load (POL) Power Supply Design Supervisor: Dr Maeve Duffy

2. Overview • Project Outline • Background • Research • Buck and Multiphase Buck Converter Simulation • Vicor V.I Chip Simulation • Buck Converter Vs V.I Chips

3. Project Outline • Objective is to compare the industry used Dc-Dc Voltage Regulator Module (VRM) the (Interleaved Buck Converter) with an alternative ‘Factorised Power’ solution. • Factorised power converters V.I Chips, PRM and VTM made by Vicor Corporation. • Pre-Regulator Module (PRM) and Voltage Transformation Module (VTM) chips.

4. Background • Operating voltages for microprocessors are getting smaller e.g. 1V. • As the operating voltage is reduced the current drawn is increased. • Higher current results in higher dissipated losses in MOSFETs and copper paths. • Challenge to maintain a constant output voltage under steady state and transient load conditions

5. Background • When the processor switches from one state to another voltage drops and spikes occur. • Vicor have proposed a factorised power solution, providing low voltage (0.8V) and high current (100A) direct from 48V input. • Compare the V.I chips and the industry used interleaved buck under steady state and transient load conditions.

6. Factorised Power Solution

7. Research • Review of VRM issues for future microprocessor requirements. • Research on the PRM and VTM V.I chips. • Review of Buck converter using Pspice. • Review of Synchronous Buck Converter • Review of the Multiphase Interleaved Buck Converter.

8. Buck Converter Simulation • Required Buck Converter Specification Input Voltage – 12V Output Voltage – 1.3V Frequency – 500KHz Output Current – 100A • Inductor and Capacitor values were calculated. • The duty cycle D was found to be 0.108, T = 2us, Ton = 0.216us

9. Buck Converter Simulation • Pspice representation of the Buck Converter circuit • The MOSFET used was 200V/120A vendor model found in the Pspice library.

10. Buck Converter Simulation Results • Vout was less than 1.3V due to the switching losses and voltage drops from the MOSFET and diodes. • By varying the ON time to 1.4us, 1.3V was obtained at the output. • The output current measured was 100A. • The output power measured was 140W. • The efficiency was found to be 93%.

11. Buck Converter Simulation Results • Current ripple was calculated to be 99.7A and the measured value obtained was 99.6A.

12. Multiphase Interleaved Buck Converter • Using the same specification as the Buck a 2-Phase Interleaved Buck was simulated.

13. Multiphase Buck Converter Simulation Results • Driving the MOSFETS 1us apart introduced the interleaving effect which is the ripple cancellation in the output capacitor. • The duty was adjusted and the correct output voltage and current was obtained.

14. Multiphase Buck Converter Simulation Results • Transient load change was also simulated and the circuit goes through transient response before it settles back down.

15. Zero Voltage Switching (ZVS) Buck-Boost Converter • The ZVS buck boost is the topology used by the PRM chip. • It is a discontinuous topology in which the inductor current IL essentially returns to zero regardless of the load. • The ZVS enables high frequency operation with high efficiency. • A switching cycle for the ZVS buck-boost consists of four phases. The Input Phase, In-Out Phase, Freewheel Phase and the Clamped Phase.

16. ZVS Buck-Boost Converter Simulation • The required specification for the ZVS Buck-Boost Input Voltage – 48V Output Voltage – 35V Output Current – 3.12A Frequency – 1.5MHz • Here is the Pspice representation of the ZVS Buck-Boost.

17. ZVS Buck-Boost Converter Simulation Results • The ZVS Buck-Boost circuit was simulated using the switching sequence below.

18. ZVS Buck-Boost Converter Simulation Results • When the circuit was simulated the output voltage was found to be 35V. • Output current 3.5A. • Output power 125W. • The efficiency was calculated and found to be 98%.

19. ZVS Buck-Boost Converter Simulation Results • A frequency of 1MHz was also simulated but was found to have bigger voltage ripple at the output. • It was also found that varying the duration of the switches, the output voltage could be controlled.

20. Sine Amplitude Converter (SAC) • This is the topology used by the VTM chip. • SAC uses a high frequency resonant tank to move energy from the input to output. • The resonant tank is formed by the resonant capacitance, inductance and leakage inductance in the power transformer windings. • MOSFETS are switched at resonant frequency and resonant current through the tank is rectified by diodes and filtered by the output capacitor. • The switching has two power transfer intervals and two 20ns energy recycling intervals.

21. Sine Amplitude Converter (SAC) Simulation • It can be implemented as a half-bride or a full-bridge resonant converter. • The required specification for the SAC is; Input Voltage – 35V Output Voltage – 1V Output Current – 100A Frequency – 1.5MHz • The resonant capacitance (CR) is 52nF and the resonant inductance (LR) is 200nH which gives a resonant frequency (FR) of 1.5 MHz

22. Sine Amplitude Converter (SAC) Simulation • Below is the Pspice representation of the half-bridge SAC.

23. Sine Amplitude Converter (SAC) Simulation Results • The transformer used is a centre tapped secondary Pspice model. • The MOSFETS were switched synchronously. • When simulated the output voltage was found to be 1V. • Output current 100A and the output power 101W . • The efficiency was found to be 99%.

24. Sine Amplitude Converter (SAC) Simulation Results • The full-bridge was also simulated. • S1 was switched with S4, S2 switched with S3.

25. Sine Amplitude Converter (SAC) Simulation Results • The output voltage was found to be 1V. • Output current 100A and the output power 105W. • The efficiency was found to be 95%.

26. Full-bridge Vs Half-bridge SAC • The full-bridge has slightly bigger voltage ripple than the half-bridge. • The full-bridge has an efficiency of 95% and the half-bridge an efficiency of 99% and therefore is slightly more efficient than the full-bridge. • If these circuits were to be built in the laboratory the full-bridge would have bigger losses and noise than the half-bridge due to the full-bridge having more switching elements. • Depends on application

27. Buck Converter Vs V.I Chips • Multiphase has ripple cancellation. • Can be redesigned to account for the effects of non-ideal active and passive components. • ZVS Buck-Boost is an efficient regulator at high frequency switching. • SAC is single phase unlike interleaved which uses multiple phases to achieve high frequency switching.

28. Buck Converter Vs V.I Chips • In terms of size the buck topology requires a bulky 15,000uF output capacitor to eliminate the ripple and the SAC requires an 80uF output capacitor. • Overall the V•I chip combination achieves high switching frequency which means using small magnetics. • Reduced size due to surface mount technology and printed circuit transformer incorporated in the SAC embodiment.

29. Summary • Microprocessor operating voltages decreasing and current is increasing. • Compare Buck Converter with ‘factorised power solution’ by Vicor Corporation. • Pre-regulator provides efficient regulation at high switching frequency. • Voltage Transformation enables high operating frequency, reduced losses and smaller size.

30. Thank you. Any Questions?