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Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis

Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis. Department of Information and Communications at K-JIST April 5th, 2000 speaker : Euiseok Kim. Contents. Introduction Preliminaries Approaches to Control Circuit Generation

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Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis

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  1. Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis Department of Information and Communications at K-JIST April 5th, 2000 speaker : Euiseok Kim

  2. Contents • Introduction • Preliminaries • Approaches to Control Circuit Generation • Controller Generation for CDFG • Timing Constrains • Experimental Results • Conclusion

  3. 1. Introduction • Asynchronous system design style becomes popular. • Existing CAD tools are restricted to synchronous system design. • ACAD tools are restricted to logic synthesis. • Unwieldy to conceive and design controllers manually. In order to overcome above problems, automaticprocess-oriented controller generation method from CDFG is presented as a part of an AHLS.

  4. R2 R4 R1 R3 + + OP1 OP2 ALU1 ALU2 R3 R2 + + OP3 OP4 ALU2 ALU1 R2 R3 2. Preliminaries DFG-UNIT Control Dataflow Graph DFG-Unit 1 CDFG-Unit 2 while 0 1 COND Node Child Block if 0 1 DFG-Unit 3 + + DFG-Unit + + endif DFG-Unit

  5. 3. Approaches to Control Circuit Generation - I • Centralized Controller • - unsuitableto asynchronous • system style • - may suffer from loss of parallelism, • difficult hazard-free synthesis • and rapid area increase. • Hardware Oriented Controller • - decomposeglobal controller • according to • hardware allocation • - may cause thesame problems • ascentralized controllers

  6. 3. Approaches to Control Circuit Generation - II • Process-Oriented Controller • - Process Controller • - Process Sequencing Controller • - Control Node Controller • - Unit Sequencing Controller

  7. 3. Approaches to Control Circuit Generation - III Example DFG-Unit 1 CDFG-Unit 2 USC while 0 1 COND. Node PSC CNC PSC Child Block if 0 1 DFG-Unit 3 PC PC PC PC USC + + DFG-Unit PC PC PC PC PSC CNC + + endif PC PC PC DFG-Unit

  8. 4. Controller Generation for CDFG - I Derivation of PC MUX MUX ReqStart+ ReqOP1+ ReqOP2t+ D FU ALU, MUL.. ReqFU+ Working Phase AckFU+ ReqWDR+ AckWDR+ MUX AckStart+ ReqOP1- ReqOP1- ReqFU- ReqWDR- D Register AckFU- AckWDR- ReqStart- AckStart- idling Phase

  9. 4. Controller Generation for CDFG - II Derivation of PSC - I start R2 R4 R1 R3 PC1 PC2 + + OP1 OP2 ALU1 ALU2 R3 R2 PC4 PC3 + + OP3 OP4 ALU2 ALU1 end R2 R3

  10. 4. Controller Generation for CDFG - III Derivation of PSC - II start Req+ AckPC1+ ReqPC1+ ReqPC2+ AckPC2+ ReqPC3+ ReqPC4+ PC1 PC2 AckPC3+ AckPC4+ Ack+ PC4 PC3 Req- ReqPC1- ReqPC2- ReqPC3- ReqPC4- AckPC1- AckPC2- AckPC3- AckPC4- end Ack-

  11. 4. Controller Generation for CDFG - IV CNC Controllers Req Ack CNC ReqCon ReqBlk AckCon AckBlk Conditional Node Child Block Flag

  12. 4. Controller Generation for CDFG - V Derivation of USC Req+ Start DFG-Unit 1 ReqBlk1+ AckBlk1+ CDFG-Unit 2 Block1 while 0 1 ReqBlk2+ AckBlk2+ Block2 Child Block if 0 1 ReqBlk3+ DFG-Unit 3 AckBlk3+ + + Ack+ DFG-Unit Block3 + Req- endif + ReqBlk1- ReqBlk2- ReqBlk3- End AckBlk1- AckBlk2- AckBlk3- DFG-Unit Ack-

  13. 4. Controller Generation for CDFG - VI • A given STG should satisfy the following four properties in order to be synthesized into a speed-independent circuit. • Boundedness • Consistency • Output Semi-Modularity • Complete State Coding Property PC, PSC, CNC and USC, which are derived through the suggested method, satisfy above fourproperties inherently !!!

  14. 5. Timing Constraints - I For correct control, designer should satisfy following three timing constraints; 1. DFU Maximum OP Fetch Delay + FU’s worst case delay + Destination Register’s input Mux’s worst case delay 2. DReg Worst case delay for Register writing delay 3. For two consecutive processes, Pi and Pj using the same hardware, the idling phase of Pishould not overlap withthe working phase of Pj. : Constraint due to bundled delay

  15. 5. Timing Constraints - II Delay Constraint 3 - I ReqFU1 1 D FU/REGISTER ReqFU2 1 PSC 0 1 0 1 1 0 1 0 PC1 PC2 1 0 AckFU1 AckFU2 1 1

  16. 5. Timing Constraints - III Delay Constraint 3 - II ReqFU1 0 D FU/REGISTER ReqFU2 0 PSC 0 1 1 1 1 0 1 0 0 1 PC1 PC2 0 1 AckFU1 AckFU2 1 1 1

  17. * * 6. Experimental Results - I 1 3 5 + + + Adder1 Adder1 Adder1 Adder : 1 Multiplier : 1 Register : 2 R1 R2 R1 2 4 6 * MUL1 MUL1 MUL1 R2 R1 R2

  18. Controllers # of Literals Area Synthesis I/O RT HO1ADD/MUL 27(3) 73.82 17.5 sec 2.09 ns HO2ADD/MUL 51(6) 146.68 204.8 sec 2.36 ns HO3ADD/MUL 98(8) 247.01 790.36 sec 3.40 ns HO1REG 21(3) 71.49 6.8 sec 2.80 ns HO2REG 47(3) 81.53 28.4 sec 1.97 ns HO3REG 73(5) 151.99 97.33 sec 2.92 ns PCCOMP 14 21.62 1.2 sec 0.71 ns PCASSI 4 15.29 0.2 sec 0.94 ns PSC2 5 14.63 0.5 sec 0.68 ns PSC4 11 20.28 2.1 sec 0.65 ns PSC8 23 31.29 53.9 sec 0.51 ns 6. Experimental Results - II Table 1. Controller Comparison between Hardware-Oriented/ Process-Oriented methods

  19. 6. Experimental Results - III Differential Equation Solver [Async’97, K. Y. Yun et al.] 1 8 2 6 9 1 7 3 8 3 10 5 9 10 4 7 2 5 4 6

  20. Controllers # of Literals Area Synthesis I/O RT AFSMALU1 43 65.86 6.3 sec 1.37 ns AFSMALU2 139 200.00 20.1 sec 2.49 ns AFSMMUL1 42 64.16 3.4 sec 1.82 ns AFSMMUL2 15 23.94 2.5 sec 1.32 ns TOTAL 239 353.96 32.3 sec 7.00 ns USC 8 18.29 0.99 sec 0.52 ns CNCWHILE 27 68.18 1.25 sec 1.57 ns PSC3 9 17.30 1.27 sec 0.44 ns PSC7 21 28.94 29.7 sec 0.36 ns PC 14  9 21.629 1.2 sec 0.71 ns TOTAL 191 327.29 34.41 sec 3.60 ns 6. Experimental Results - IV Table 2. Controller Comparison between Hardware-Oriented/ Process-Oriented methods for Differential Equation Solver [Async’97 & 3D, K. Y. Yun et al.]

  21. 6. Experimental Results - V Simulation result I - Controllers

  22. 6. Experimental Results - VI Simulation result II - Datapath

  23. 7. Conclusion • In this paper, we suggest an automatic asynchronous controller generation method based on process-oriented method having the following noticeable features; • to present a systematic and hierarchical way • to produce STGs satisfying four properties for SI-circuit synthesis • to be efficient in the points of area and performance • to be useful for controller generation of large initial specification Consequently, process-oriented method can be used as an alternativeapproach to asynchronous controller generation.

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