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CS 2204

CS 2204. Lab 8. Experiment 4 - 5. Digital Logic and State Machine Design. Spring 2008. Lab 8 Outline Presentation Digital product development overview Digital Product Development Component selection for a PCB  TT L LS SSI chip usage Component selection for a chip

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CS 2204

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  1. CS 2204 Lab 8 Experiment 4 - 5 Digital Logicand State Machine Design Spring 2008

  2. Lab 8 Outline • Presentation • Digital product development overview • Digital Product Development • Component selection for a PCB  TTL LS SSI chip usage • Component selection for a chip  Xilinx component usage • Analysis of Block 1 of the term project • A machine playing strategy • Xilinx sequential circuit components • Individual work • Experiment 4 • Develop the Rightmost Largest Display circuit of the Ppm term project • Experiment 5 • Develop the BCD up counter in the Random Digit Generation Subsubblock of the Ppm term project CS 2204 Spring 2008

  3. PCB • Developing a new PCB Which chips and how many ? TEST : Simulating by applying input combinations, test vectors, may not be possible. It may be coarse grain simulation 1) Development Cycle on Computers DESIGN TEST MODIFY During testing if you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors Major error : Redesign Major error : Redesign or terminate the project due to TTM 2) Dev. Cycle with off-the-shelf chips Mount : Chips are mounted on bread/boards and wired Mount Test Modify Test : apply test vectors to the chips Modify : chip mounting/wiring is changed and tested or a simple design change is made on computers, simulated, then FPGAs are programmed and tested Major error : Redesign or terminate the project due to TTM 3) Dev. Cycle on prototype PCB Fabricate PCB at a fabrication facility, mount chips and other components Fabricate Test Modify Apply test vectors to the PCB Modify means chip mounting/wiring is changed and tested CS 2204 Spring 2008

  4. Developing a digital product • A new PCB • Which chips and how many is determined by • The application (major operations) • Available chips of the technology chosen • Besides speed, cost, power, etc. : design goals CS 2204 Spring 2008

  5. Use these as much as possible • CS2204 components • Available chips for a new PCB TTL LS chips Lectures, homework, exams Generic chips Lectures, homework, exams Flip-flops Gates Flip-flops Popular digital circuits Gates Popular digital circuits AND OR NOT NAND NOR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … D JK High-density chips To save time, space, power. weight,… CS 2204 Spring 2008

  6. Use higher density chips as much as possible Try not to use these SSI chips • CS2204 components • Available chips for a new PCB TTL LS chips Lectures, homework, exams Generic chips Lectures, homework, exams Flip-flops Gates Flip-flops Popular digital circuits Gates Popular digital circuits AND OR NOT NAND NOR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … D JK High-density chips CS 2204 Spring 2008

  7. From ON Semiconductor LS TTL Data Manual From Texas Instruments Digital Logic Data Book Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout NAND-Gate Chips 74LS00 4 2-input NAND gates 74LS10 3 3-input NAND gates 74LS20 2 4-input NAND gates 74LS30 1 8-input NAND gate CS 2204 Spring 2008

  8. From Texas Instruments Digital Logic Data Book Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout NOR-Gate Chips 74LS02 4 2-input NOR gates 74LS27 3 3-input NOR gates CS 2204 Spring 2008

  9. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout Inverter-Gate Chips 74LS04 6 inverters From ON Semiconductor LS TTL Data Manual CS 2204 Spring 2008

  10. From ON Semiconductor LS TTL Data Manual From Texas Instruments Digital Logic Data Book Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout AND-Gate Chips 74LS08 4 2-input AND gates 74LS11 3 3-input AND gates 74LS21 2 4-input AND gates CS 2204 Spring 2008

  11. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout OR-Gate Chips 74LS32 4 2-input OR gates From ON Semiconductor LS TTL Data Manual CS 2204 Spring 2008

  12. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout EX-OR-Gate Chips 74LS86 4 2-input EX-OR gates From Texas Instruments Digital Logic Data Book CS 2204 Spring 2008

  13. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout AND-OR-Invert-Gate Chips 74LS51 Dual AOI Network From Texas Instruments Digital Logic Data Book CS 2204 Spring 2008

  14. TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout Try not to use SSI chips EX-NOR-Gate Chips 74LS266 4 2-input EX-NOR gates CS 2204 Spring 2008

  15. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout D-FF Chips 74LS74 2positive-edge triggered D Fs From ON Semiconductor LS TTL Data Manual CS 2204 Spring 2008

  16. Try not to use SSI chips • TTL LSSSI Chips Used This Semester • They have less than 10 gates according to the A Brief Look at Semiconductor Technology handout J-K-FF Chips 74LS112 2negative-edge triggered J-K Fs CS 2204 Spring 2008

  17. We need : 1 inverter 2 2-input AND gates 1 2-input OR gate a NOT AND b OR 1 74LS04 with 6 inverters, 5 inverters unused 1 74LS08 with 4 2-input AND gates, 2 gates unused 1 74LS32 with 4 2-input OR gates, 3 gates unused a AND c Total : 3 chips used, 10 gates unused y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New PCB • By using TTL LSSSI chips with AND, OR, NOT,… gates • The 2-to-1 MUX Try not to use SSI chips Which TTL components ? TTL LS SSI Chip Usage ? CS 2204 Spring 2008

  18. 174LS157 4-bit 2-to-1 MUX Total : 1 chip used, 0 gates unused • Implementing a Combinational Circuit on a New PCB • The 2-to-1 MUX • Try not to use SSI chips to implement combinational circuits • Use higher density chips : 74LS157 TTL LSMSI chip : 4 2-to-1 MUXes • One chip has four 2-to-1 MUXes ! 0 0 0 0 b c 0 0 0 Which TTL components ? a y From ON Semiconductor LS TTL Data Manual CS 2204 Spring 2008

  19. We need : We need : 2 inverters 5 2-input AND gates 1 5-input OR gate 2 inverters 5 2-input AND gates 4 2-input OR gates No TTL chip with 5-input OR gates OR OR OR OR • Implementing a Combinational Circuit on a New PCB • By using TTL LSSSI chips with AND, OR, NOT,… gates Try not to use SSI chips TTL LS SSI Chip Usage ? Which TTL components ? Implement it with 4 2-input OR gates 2-bit Unsigned Binary Comparator From Handout 5 CS 2204 Spring 2008

  20. We need : 2 inverters 5 2-input AND gates 4 2-input OR gates 1 74LS04 with 6 inverters, 4 inverters unused 2 74LS08 with 4 2-input AND gates, 3 gates unused 1 74LS32 with 4 2-input OR gates, 0 gates unused Total : 4 chips used, 7 gates unused • Implementing a Combinational Circuit on a New PCB • By using TTL LSSSI chips with AND, OR, NOT,… gates Try not to use SSI chips TTL LS SSI Chip Usage ? Which TTL components ? 2-bit Unsigned Binary Comparator From Handout 5 CS 2204 Spring 2008

  21. Implementing a Combinational Circuit on a New PCB • 2-bit Unsigned Binary Comparator • Try not to use SSI chips to implement combinational circuits • Use higher density chips : 74LS85 TTL MSI chip : a 4-bit Unsigned Binary comparator • We also need a 74LS32 OR-gate SSI chip ! • Two chips used ! CS 2204 Spring 2008

  22. 1 74LS85 4-bit Unsigned Comparator 1 74LS32 with 4 2-input OR gates, 3 gates unused Total : 2 chips used, 3 gates unused • Implementing a Combinational Circuit on a New PCB • 2-bit Unsigned Binary Comparator • Try not to use SSI chips to implement combinational circuits a 0 d c b 0 0 0 z 0 74LS85 0 1 CS 2204 Spring 2008

  23. We need : 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3J-K FFs • Implementing a Sequential Circuit on a New PCB • By using TTL LS SSI chips with D, J-K, AND, OR, NOT,… gates Try not to use SSI chips TTL LS SSI Chip Usage ? Which components ? CS 2204 Spring 2008

  24. We need : 2 inverters 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 8 2-input OR gates 3 negative-edge triggered J-K FFs OR OR OR • Implementing a Sequential Circuit on a New PCB • By using TTL LS SSI chips with D, J-K, AND, OR, NOT,… gates Try not to use SSI chips We need : TTL LS SSI Chip Usage ? 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3 positive-edge triggered J-K FFs Which components ? There is no positive-edge triggered J-K FF chip ! We need one more inverter to invert the clock There is no 3-input OR-gate chip ! We implement it with 2-input OR gates CS 2204 Spring 2008

  25. Here there is no choice ! We have to useSSI chips ! 1 74LS04 with 6 inverters, 4 inverters unused 1 74LS08 with 4 2-input AND gates, 0 gates unused 2 74LS11 with 3 3-input AND gates, 0 gates unused 1 74LS21 with 2 4-input AND gates, 1 gate unused 2 74LS32 with 4 2-input OR gates, 0 gates unused 2 74LS112 with 2 negative-edge triggered J-K FFs, 1 FF unused Total : 9 chips used, 5 gates and 1 FF unused • Implementing a Sequential Circuit on a New PCB • By using TTL LS SSI chips with D, J-K, AND, OR, NOT,… gates Try not to use SSI chips We need : 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3 positive-edge triggered J-K FFs CS 2204 Spring 2008

  26. Chip • Developing a new chip Which components and how many ? TEST : applying input combinations, test vectors, and simulating 1)Development Cycle on Computers During testing If you see MODIFYING hardware to optimize it is possible, do that after you correct logic and timing errors. Then, test again to see if your minimization has logic/timing errors DESIGN TEST MODIFY Major error : Redesign Major error : Redesign or terminate the project due to TTM Mount : FPGAs are mounted on bread/boards, wired and programmed 2)Development Cycle with FPGA chips Test : apply test vectors to FPGAs Mount Test Modify Modify : either FPGA mounting/wiring is changed or a simple design change is made on computers, simulated, then FPGAs are programmed and tested Major error : Redesign or terminate the project due to TTM 3)Development Cycle on prototype chip Fabricate chip by sending a GDSII file to a fabrication facility : tape out Fabricate Test Apply test vectors to the chip CS 2204 Spring 2008

  27. Developing a digital product • A new chip • Which gates/FFs and how many is determined by • The application (major operations) • Available components of the technology chosen • Besides speed, cost, power, etc. : design goals CS 2204 Spring 2008

  28. Use these as much as possible • CS2204 Components • Available components for a new chip Xilinx components Labs Generic components Lectures, homework, exams Flip-flops Gates Flip-flops Popular digital circuits Gates Popular digital circuits ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK T SR … ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register … AND OR NOT NAND NOR … D JK High-density circuits To save time, space, power. weight,… CS 2204 Spring 2008

  29. a NOT AND b 1 inverter 2 2-input AND gates 1 2-input OR gate OR a AND c Total : 4 gates used y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a NewChip • By using generic components that are AND, OR, NOT,… • The 2-to-1 MUX Which components ? CS 2204 Spring 2008

  30. 2 inverters 5 2-input AND gates 1 5-input OR gate Total : 8 gates used 2-bit Unsigned Binary Comparator From Handout 5 • Implementing a Combinational Circuit on a NewChip • By using generic components that are AND, OR, NOT,… Which components ? CS 2204 Spring 2008

  31. 1 inverter 4 2-input AND gates 6 3-input AND gates 1 4-input AND gate 4 2-input OR gates 2 3-input OR gates 3J-K FFs Total : 21 components used • Implementing a Sequential Circuit on a NewChip • By using generic components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 9 Which components ? CS 2204 Spring 2008

  32. Lab design Use Xilinx macros as much as possible Try not to use these components • CS2204 Components • Available components for a new chip Xilinx components Labs Generic components Lectures, homework, exams Gates Flip-flops Popular digital circuits Gates Flip-flops Popular digital circuits D T JK AND OR NOT NAND NOR… ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register… AND OR NOT NAND NOR… D JK T SR ADDer Comparator Multiplexer DeMux Decoder Encoder ALU Counter Register… High-density chips CS 2204 Spring 2008

  33. 1 inverter, INV 2 2-input AND gates, AND2 1 2-input OR gate, OR2 Total : 4 gates used a NOT AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • The 2-to-1 MUX Which Xilinx components ? CS 2204 Spring 2008

  34. a NOT Do not design your own 2-to-1 MUX AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • The 2-to-1 MUX Use them Xilinx already has 2-to-1 MUXes CS 2204 Spring 2008

  35. 1 Xilinx M2_1 MUX Total : 1 component used a NOT AND b OR a AND c y(a, b, c) =a.b + a.c • Implementing a Combinational Circuit on a New Chip • The 2-to-1 MUX • Xilinx already has 2-to-1 MUX macros • M2_1 Which Xilinx components ? CS 2204 Spring 2008

  36. 2 inverters, INV 5 2-input AND gates, AND2 1 5-input OR gate, OR2 Total : 8 gates used • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… Which Xilinx components ? 2-bit Unsigned Binary Comparator From Handout 5 CS 2204 Spring 2008

  37. Do not design your own Comparator • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are AND, OR, NOT,… • 2-bit Unsigned Binary Comparator Use them Xilinx already has Comparators You need an extraOR gate besides the comparator CS 2204 Spring 2008

  38. 1 Xilinx 74_L85 Comparator, X74_L85 1 Xilinx 2-input OR gate, OR2 Total : 2 components used • Implementing a Combinational Circuit on a New Chip • 2-bit Unsigned Binary Comparator • By using Xilinx comparators Which Xilinx components ? CS 2204 Spring 2008

  39. 1 inverter, INV 4 2-input AND gates, AND2 6 3-input AND gates, AND3 1 4-input AND gate, AND4 4 2-input OR gates, OR2 2 3-input OR gates, OR3 3 positive-edge triggered J-K FFs, FJKC Total : 21 components used • Implementing a Sequential Circuit on a New Chip • By using Xilinx components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 9 Which components ? CS 2204 Spring 2008

  40. We have to design our own sequence detector • Implementing a Combinational Circuit on a New Chip • By using Xilinx components that are D, J-K, AND, OR, NOT,… • The sequence detector from Handout 9 Xilinx does not have this sequence detector The design with 21 components isimplemented CS 2204 Spring 2008

  41. Analysis of the Term Project • The term projectblack-box view • The term projectoperation diagram • The term projectblack box partitioning CS 2204 Spring 2008

  42. The Term Project, Ppm • The black-box view • Ppm is sequential (not combinational) • A large number of FFs are used ! • Ppm is a digital system • We need to partition the Ppm based on major operations • We have to obtain the operation diagram From page 2 of the Term Project Handout CS 2204 Spring 2008

  43. LD6-LD8 on the FPGA board show the current state Ppm Input/output relationship From page 8 of the Term Project Handout Ppm operation diagram CS 2204 Spring 2008

  44. core core core core core non-core • The Ppm Term Project • Ppm is a digital system ! • The Ppm term project partitioning • First partitioning of the digital system • Control Unit • Data Unit • Second partitioning (Data Unit partitioning) • Interfacing to the input/output devices • Handling human player’s play • Controlling display operations based on game rules • Calculating new player points • Determining the machine player play CS 2204 Spring 2008

  45. The Ppm Digital SystemPartitioning M1 M2 From page 9 of the Term Project Handout CS 2204 Spring 2008

  46. The term project black box partitioning • Sixschematics for sixblocks • Block 1 : Control Unit : ppm1.sch schematic file • Block 2 : Input/Output : ppm2.sch schematic file • Block 3 : Human Play : ppm3.sch schematic file • Block 4 : Play Check : ppm4.sch schematic file • Experiment 1 is on a circuit in this block • Block 5 : Points Calculation : ppm5.sch schematic file • Block 6 : Machine Play : ppm6.sch schematic file • The Machine Play Block uses all other blocks except the Human Play Block CS 2204 Spring 2008

  47. Digital Systems • A digital systemperformsmicrooperations • A digital systemconsists of digital circuits • A digital system consists of • A data unit (datapath) • It performs microoperations • A control unit • It controls the datapath CS 2204 Spring 2008

  48. Digital Systems • This first partitioning of a digital system is universal • A microprocessor is a digital system • An iPhone is a digital system • A computer is a collection of digital systems CS 2204 Spring 2008

  49. Digital Systems • The data unit has registers, ALUs and buses to perform microoperations • Registers keep (store) data (operands and results) • Arithmetic Logic Units (ALUs) perform additions, subtractions, multiplications, ANDS, ORs, etc. • Buses interconnect registers and ALUs CS 2204 Spring 2008

  50. Digital Systems • The Control Unit (Sequencer) • The control unit determines the sequence of microoperations based on the status signals • The control unit goes through states • In each state, it enables the microoperations of that state to happen in the data unit based on the status signals ► Microoperations must start at the right time with correct inputs and end at the right time with correct outputs  We should notlose data and we should not use old data ► Glitches, gate delays must be accounted for  When we design it, we account for every possible gate delay CS 2204 Spring 2008

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