MCC-PRR: Overview of MCC Updates Since FDR

1. MCC-PRR: Overview of MCC Updates Since FDR Giovanni Darbo / INFN - Genova E-mail: Giovanni.Darbo@ge.infn.it

2. Brief MCC History 1997: Specification of the ATLAS Pixel Detector System Architecture -> Two chips on module: FE + MCC.Ref.:http://www.ge.infn.it/ATLAS/Electronics/Demonstrator-20/MCMSpec.2.0.pdf 1998 (MCC-AMS): First non rad-hard implementation, AMS technology, ReceiveFIFO sizes 32 words, many demonstator modules built. 2000 (MCC-D): DMILL implementation of AMS design. Chip size 50% larger, very low yield (no one of the packaged & tested chip fully functional). Project abandoned, move to DSM technology. 2002 (MCC-I1): Complete redesign of the MCC, increase ReceiverFIFO to 128 words, added delay line block for FE calibration, added features for better module debugging. Many modules (~100) built and characterised. Found very radiation resistant (chip working up to 60 Mrad). FDR passed (12/02). 2003 (MCC-I2): Final design, improved SEU tolerance by adding replica logics in most of the critical parts and redundant hit encoding in FIFO’s. Design error (no read back configuration data from FE) -> FE-I2.1. December 2003: 6 wafer tested - 2666 good chips!

3. Pixel Module Controller Chips MCC-AMS MCC-I1 MCC-I2 Technology 0.8µm 0.25 µm 0.25 µm Routing layers (1P)/2M (1P)/5M (1P)/5M No. Stand.Cells. 17.922 29.000 68.000 No. Transistors 363 k 650 k 880 k Area (mm2) 66.8 25.4 35.2 No. Of Test Vectors 0.6 M 1.5 M 3.0 M MCC-I2 MCC-AMS MCC-I1 MCC-D2 2003 2002 1998 2000

4. What the Reasons MCC-I1  MCC-I2 • Bug Fixes. • Unfortunately a major bug have been introduced in the MCC-I2 which prevents readout of FE configuration. • Easily fixed from in MCC-I2.1. • Increase SEU tolerance • Most of the critical logics uses tree replica with majority decision. • Implications: • Functional spec changes: see Roberto’s talk). • SEU improvement: see Guido’s talk. • IDD, Timing, Size: next slides.

5. MCC-I1 vs MCC-I2 • No. of Std Cells: 67,919 • No. of nets: 69,501 • No. of Inv1: 35,130 • No. of transistors: 880K • Dimensions: 6840 x 5140 mm2 • No. of Std Cells: 33,332 • No. of nets: 34,368 • No. of Inv1: 18,834 • No. of transistors: 660K • Dimensions: 6380 x 3980 mm2

6. IDD • Dynamic IDD scales with the number of standard cells: ~30% more. This is observed in the measures done by Delta™ on wafers (see fig.) • We have increased the VDD/GND busses to compensate the more current. We had to balance between chip size (Flex Hybrid constraint) and power/standard cells increase.

7. Power and Ground Resistance

8. Timing • The MCC-I2 has been synthesized with the same timing parameters as MCC-I1 (400 ps for clock skew, 70 MHz nominal CK frequency). • Clock tree has been generated by Silicon Ensemble™ and Pearl static analysis gives similar results as MCC-I1: 100 ps hold time (best case) and master clock tree distribution: MCC-I1MCC-I2 Max. transition time at leaf pins: 0.341 ns 0.309 ns Min. insertion delay to leaf pins: 2.511 ns 3.080 ns Max. insertion delay to leaf pins: 2.984 ns 3.423 ns Max. skew between leaf pins: 0.473 ns 0.343 ns

9. The SMPW1 Wafer 3 1 4 2 6 5 8 7 • 134 potentially good reticles/wafer • 536 (562) potentially good MCC-I2/wafer • 2666 good MCC-I2

10. Design Validation • Verilog behavioural validation: • The MCC behavioural model is first validated using using SimPix scripts (about 2 M clock cycles). Validation is made by SimPix by comparing Verilog results with expected data from a c++ model of the MCC. • In case of anomalies flagged by SimPix, the designer check results by hand. • Synthesized netlist is passed trough SimPix analysis for final check. • Most of the SimPix scripts written for design validation are then used for chip test: • Special designed hardware tester: MCCex • Logic State Analyser: Agilent 16700 • Production test: external contractor (Delta - DK).

11. SimPix block diagram Clock Generator Detector response and LVL1 simulator FE behavioral simulation MCC behavioral simulation MCC input preparation MCC or Verilog model MCC command generator MCC output decoding Time oriented database Automatic analysis

12. Standard SimPix operations In the standard configuration SimPix compares the output of a true MCC or of a Verilog model with the output of a behavioral C++ MCC model. The input is taken from a Geant simulation and modified by a C++ FE model. Module selector C++ FE Model MCC Geant Module Hits Automatic Comparison Random Hits/Noise Generator C++ MCC Model

13. Hits C++ MCC LVL1 LVL1 MCC LVL1 FE out C++ MCC out Anomalies MCC out

14. SimPix Example: Event Dump

15. Chip Test & Validation • Single MCC-I2 chips packaged and tested: • To study critical timing aspects: SimPix with logic state analyzer. Validation of the chip can be done trough SimPix or comparing two chips. • To have longer and faster test vectors runs: MCCex. Example of event R/O error happening at low VDD

16. The MCC Exerciser It’s a 6U VME card developed for testing the MCC-AMS. It provides 20 bi-directional 8 Mbit deep channels, which can be used to send inputs to the MCC or receive outputs. Data are stored in a VME accessible RAM. Pro: • Deep memory. • Fast data download/upload. Cons: • Designed for MCC-AMS; no DTO2 and 80 Mbit/s support. • Clock fixed at 40 MHz. 2x8 Mbit Memory Card MCC VME Interface

17. MCC-I2: R/O Bug RunMode Line to add VDD Line to cut RunMode Because of an error in a logical condition of the source code describing the MCC-I2, it is impossible to read configuration data from FE’s. The problem can be easily patched with a cut of an enable line and its connection to VDD (see fig.) • Few MCC-I2 modified by FIB (next slide). • Spinoff wafers (6 wafer partially processed, no metallizations) with M2 mask modified: 6 Production Wafers.

18. “Surgical” Care for MCC-I2 Opening to align GDS with chip M4 (all. Oriz) & LM (all. Vert) • Used Focussed Ion Beam (FIB) to cut a M2 (40µm) trace and to connect one side of it VDD (M1) by deposition of W. • Some 25 MCC-I2 fibbed to test and produce modules. Cut M2 Weld M2-M1

19. MCC-I2 / FH5.x / FE-I2.1 Many modules built with MCC-I2.fib Genova • 2 MCC-I2 fibbed + FE-I1 (1 used at test beam) • 1 MCC-I2 + FE-I1 • 5 MCCI2 fibbed + FEI2.1 (2 irradiation +1 fast extraction) Bonn • 7 MCCI2 fibbed + FEI2.1 (2 irradiation) LBL • 3 MCC-I2 fibbed + FE-I1 (~1 test beam) • 5 MCC-I2 fibbed + FEI-2.1 (3 irradiation)

20. Irradiation at PS & High Intesity Beam Single chips and modules tested at PS and at the high intensity beam. Chips can sustain 60 Mrad integrated dose. SEU and SEE effects greatly improved from MCC-I1. R/O doesn’t hung-up due to SEU. Results from Guido’s talk 7 Modules @ PS

21. Critical Aspect: VDD Corruption of event R/O happens when modules are operated at VDD slightly below the nominal VDD. Some modules showed even corruption at ≥ 2 V. Extensive investigation and test carried on from last summer…. Left fig.: typical event corruption, extra hits on some columns and inefficiencies on others. Inefficiencies Extra hits Extra LV1

22. DVDD Threshold VDD measured on pigtail, MCC VDD is ~ 150 mV lower

23. MCC-I2 / MCCex VDD is on MCC

24. VDD @ Irradiated Modules Several modules irradiated to 55 Mrad tested for R/O corruption vs. VDD. • Rather wide spread of error free VDD threshold (between 2.15 V and 2.4 V measurerd on the pigtail, which is 150 mV higher than MCC) • Before irradiation those modules shown already rather high VDD threshold in the PS setup (higher than other modules tested in the lab). GE-26 T=0ºC GE-27 T=0ºC

25. Consideration on VDD Test summary • Not irradiated modules tested in the lab at low temperature works correctly at nominal 2 V VDD. • Single chip MCC tested in the lab with MCCex works around 1.8 V before irradiation and near 1.9÷2.0 V after 60 Mrad irradiation (not tested before irradiation). • Single chips and modules have a temperature dependence. Lower temperature is better. • Some modules after irradiation need a VDD sensibly higher than nominal. What to do • Added a VDD sweep in the production test: sort chips for B_layer • Irradiate MCC having different VDD threshold (V=1.75 and V=1.9) and correlate before/after irradiation. Conclusion Sort chip for B_layer, rise VDD as dose rise… take good physics!

26. Conclusions • MCC-I2.1 is qualified for the use in ATLAS. • We have enough good MCC-I2.1 for the 3 layer Pixel Detector. • Listen to • Specification changes update. • SEU upset data (it was slightly at the limit for the MCC-I1). • Production test: specification and results. Then… we wait for the Green light to use them !