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SVD2.5/3.0 electronics

SVD2.5/3.0 electronics. GDL time resolution (discussions with M.Pernicka) SVD2.5/3.0 readout conceptual design. Summary of requests on APV hold timing and resolution (from M.Pernicka). Hold signal latency should be less than 3.7 m s at APV (192-32 cells) x 1/42.33MHz = 3.780 m s

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SVD2.5/3.0 electronics

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  1. SVD2.5/3.0 electronics • GDL time resolution (discussions with M.Pernicka) • SVD2.5/3.0 readout conceptual design M. Hazumi at SVD3 meeting

  2. Summary of requests on APV hold timing and resolution (from M.Pernicka) • Hold signal latency should be less than 3.7ms at APV • (192-32 cells) x 1/42.33MHz = 3.780ms • no problem for SVD2.5 (confirmed by Iwasaki-san) • for SVD3 under discussion with Iwasaki-san • strongly prefers to have good timing resolution (~3ns) Why ?  see the next 3 slides from M.Pernicka M. Hazumi at SVD3 meeting

  3. M.Pernicka The time between the trigger information of the TOF, if exists (or other time references), and the clock synchronised trigger for the APV25 can be measured and transmitted to the FADC system. Assuming that the signal peaks in the desired time window, we can expect a certain relation between the samples S1, S2, S3 of the shaped signal.By using 6 samples, we could possibly detect and mostly correct pile-ups for S1, S2, and/or S3 from a signal before or after the wanted signal. S1 S2 S3 shaping time like that, S1<S2>s3 M. Hazumi at SVD3 meeting Manfred Pernicka, Hephy , Vieanna

  4. M.Pernicka Reduction factor in compare VA1TA and APV25 VA1TA shaping time 800ns >2400ns 2400ns above threshold = accepted as signal Cost: something APV shaping time 50ns >150 ns Reduction factor ~16 150 ns above threshold Cost: nothing but requires the APV Reduction factor ~10-8 Using time information of signal and trigger to clock 150 ns ~15 – 20 ns Finalreduction~160-108 (Reduction factor without factor for shorter Si strips) M. Hazumi at SVD3 meeting Manfred Pernicka Hephy, Vienna

  5. M.Pernicka Theoretical: if we have more than 1 layer, we could combine stripes with the same time and in most cases we do know, which trake belongs to the trigger in reason of time between real trigger and synch. trigger t=n+1 t=n t=n t=n+1 t=n t=n+1 M. Hazumi at SVD3 meeting

  6. My comments • Reading out 6 samples takes longer time • single-peak mode: GDL latency + ~7us (see next slide) • 6 samples: additional delays at least 128 x 5 x 25ns = 16us • Reading out 3 samples • time resolution ?  can be checked by analyzing testbeam data ? • Need more studies to know the real gain M. Hazumi at SVD3 meeting

  7. follow-up • Can we have good GDL timing resolution for SVD2.5 ? • Present timing resolution with ToF (ECL) ~5ns (~30ns) (should consult Ozaki-san to know more accurate number). Some studies needed to know background-dependence. • Less than 10% of hadronC events with ECL timing alone. • ToF timing logic requires (TOF hits).and.(CDC hits), but no geometrical matching is used. Geometrical matching was studies (MC) at the beginning of Belle exp. and was not so useful. However, some proper geometrical matching may be useful if background is high. • Can we have good GDL timing resolution for SVD3 ? • Kichimi-san said ToF would be too noisy at SuperB. • Nishida-san agreed to think (conceptually) about possible electronics for TOP readout to provide good-timing trigger. (info from Iwasaki-san) M. Hazumi at SVD3 meeting

  8. Readout Latency Measurement (Base clock = 40MHz) ~0.85s APSP circuit causes a large jitter (35 base clocks0.875 s for 40MHz) • Time at which ADC receives the analog level of the last strip • Here T=0 is the trigger timing. • 35x4 clk APSP (max.) • 12 clk header etc. • clk 128 strip analog level • 12 clk ? • ------------------------------------------ • 292 clk • 292clk x 25ns = 7300s 7.29s (some offset) This measurement enables us to determine the basic trigger scheme (see slides below)

  9. toward SVD2.5 readout conceptual design • SVD2.5 VA1TA readout (Summary of slides on Mar.23) • SVD2.5 APV readout M. Hazumi at SVD3 meeting

  10. Summary of slides on Mar.23 • SVD2.5 VA1 readout needs 1 PC / ADCTF • even with this, the bandwidth seems marginal. Needs more studies. • at 15% occupancy (~ 3  now) • data size = 31.2kB/event • event processing rate ~ 3.3 kHz • deadtime ~ ? • frontendbackend: 7.8% • rest: FADC keeping busy by instantaneous high rate M. Hazumi at SVD3 meeting

  11. M. Hazumi at SVD3 meeting

  12. Requirements on SVD2.5 readout • data processing speed greater than 3 kHz • dead time less than 5% ? at 3 kHz trigger rate • data size with a manageable level (~Y MB/s) • storage capability = 250MB/s (max) • SVD2.5 VA1TA raw data size = 6kB/event/FADC x 3 kHz x 32FADCs = 576MB/s  86MB/s with sparcification • occupancy is assumed to be ~ 15% • SVD2.5 APV25 raw data size (no-striplet option) = (4-24)kB/event/FADC x 3 kHz x 6FADCs = (72-432)MB/s  (3-?) MB/s with sparcification • occupancy is assumed to be ~ 10% x 3 / 8 = 4% M. Hazumi at SVD3 meeting

  13. Solution for SVD2.5 readout1) VA part • 48 VA ladders • 192 Cat 5 cables (4ch/cable) • 32 FADCs (24ch/FADC) • 6kB raw data/FADC • 32 PCs (1 PCI card/PC) • dual XEON 3.6GHz • intel compiler • software using Posix thread • PCI: 75MB/s max.  up to 12kHz for 6kB/FADC M. Hazumi at SVD3 meeting

  14. Solution for SVD2.5 readout2) APV part • 6 APV ladders (normal DSSDs) • 24 Cat 6(?) cables (4ch/cable) ? • 6 FADCs (16ch/FADC ) in an additional crate • peak mode: 4kB raw data/FADC • 3 [6] samples: 12kB [24kB] • 6 PCs (1 PCI card/PC) • dual XEON 3.6GHz • intel compiler • software using Posix thread • PCI: 75MB/s max.  up to 18kHz for 4kB/FADC  up to 6kHz for 12kB/FADC •  up to 3kHz for 18kB/FADC assuming no data reduction inside FADC M. Hazumi at SVD3 meeting

  15. Schematics of the ADC with the possibility of single channel processing and output with data for trigger processor (module exists) Every output of a fast signal like data, clock or strobe is connected only to one input. Serial termination. 32 Bit Address/data bus VME protocol Altera P 1 4 times 10 bit data 36 Input 9-RJ45 connectors 9 lines with information for trigger proc. 4 ADC Dau. Altera Daughter 9 inputs 9 data proc + FIFO’s 64 (or 32 bit) bit data bus 40 MHz+4 control lines Transmit crate clock, control signals and event number from TTM system and a serial output for every input (36) clocks with adjustable phase Altera daughter with final FIFO Fast Control bus P 2 Delayed clock and control sig. distributor, VME control Altera P 3 Fast data transfer to PCI protocol is open 32 or 64 bit M. Hazumi at SVD3 meeting

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