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SNS Timing Master LA-UR-03-3377 Eric Bjorklund

SNS Timing Master LA-UR-03-3377 Eric Bjorklund. Basic Characteristics. Event System. 256 events possible. 25 events currently in use. ~5 millisecond machine cycle. 60 Hz. Option to go to 120 Hz. when second target added. 10 second super-cycle. Clock synchronized with ring RF.

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SNS Timing Master LA-UR-03-3377 Eric Bjorklund

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  1. SNS Timing Master LA-UR-03-3377 Eric Bjorklund

  2. Basic Characteristics • Event System. • 256 events possible. 25 events currently in use. • ~5 millisecond machine cycle. 60 Hz. • Option to go to 120 Hz. when second target added. • 10 second super-cycle. • Clock synchronized with ring RF. • Ring RF is 1.057767 Mz at 1 GeV • Clock is 32 X Ring RF

  3. GPS Timing System Components Event RTDL Link SNS Time Stamps Beam data Experimental Halls Master Timing IOC RF Gates Extraction Kickers TxHV Gates Timing SNS Real 10 MHz Slave Time Data Crystal (V124S) Link Osc. Master High resolution timestamps Machine Modes Machine SNS Event X32 PLL Protection Link (33 MHz) System Master Ring RF SNS Timestamps Remote Reset Synchronous ISR’s ICS IOC's Timing Reference Generator AC SNS Utility Module Line Beam Delay Beam Phase Micro pulse width Macro pulse width LEBT *4 PLL Chopper (64 MHz) Neutron Choppers SNS Time stamps Delays Gates Triggers Diagnostics Timing System Subsystem Hardware Hardware Timing System Users Experimental Systems

  4. Two Transmission Links • Event Link • Transmits the timing events that define a machine cycle. • Each event is 8 bits plus parity (256 events maximum). • Clock is variable and derived from the ring revolution frequency (32 * Frev). • Events 0 – 63 are generated by the timing system hardware. • Events 64 – 255 are generated by software (no fixed times). • Real-Time Data Link (RTDL) • Transmits machine parameters and data prior to every new cycle. • 128 frames possible (expandable to 255). • Each frame contains an 8-bit frame number, 24-bits of data, and an 8-bit CRC. • Clock is 10 MHz.

  5. Sample RTDL Data Frames Frame NumberData 1 – 3 Time of day 4 Event link period 5 MPS mode 6 60 Hz phase error 7 Beam Width 15 IOC Reset Address 17 Pulse Flavor 18-21 RF Gate Widths 24 Previous Pulse Status 25 Cycle 255 24-bit CRC (calculated)

  6. VME Bridge GPS Interface Utility Module RTDL Master (V105S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) RTDL Input Module (V206S) (Reserved) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Line Synch Module Processor (Reserved) Utility Module Event Link Master (V123S) Event Link Input Module (V101S) Event Link Input Module (V101S) Event Link Input Module (V101S) Event Link Input Module (V101S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Trigger Module (V124S) Frequency Counter Event Monitor VME Bridge 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 Timing Master Crate Layout

  7. Event Link Generator Hardware • Event Link Master Module (V123S) • VME Module. • Generates event link carrier (~17 Mhz). • Accepts, prioritizes, and transmits “hardware” and “software” events. • Event Link Input Module (V101S) • VME Module for generating “hardware” events. • Communicates with the event link master module over the VME P2 backplane. • Hardware events generated from TTL inputs to the V101S • 16 events per module.

  8. RTDL Generator Hardware • RTDL Master Module (V105S) • VME Module • Generates the 10 MHz RTDL Carrier Signal and the RTDL frames. • RTDL Input Module (V206S) • VME Module. 8 frames per module. • Stores the data frames to be sent each cycle on the RTDL. • Communicates with the RTDL master module over the VME P2 backplane.

  9. Additional Modules • Timing Reference Generator • Double-Wide VME module. • Provides the 60 Hz “Cycle-Start” signal to the event link master module (V123S). • Uses a PLL to track the AC line zero-crossing and “smooth out” power grid frequency fluctuations. • Resolves the “conflict of interest” between power supplies that need to be “line locked” and the neutron choppers’ need for stable timing. • Frequency Counter • VME Module in the Timing Master crate. • Used to monitor the frequency of the event link clock. • Frequency is broadcast on the RTDL and sent to the timing reference generator to compensate for changes in the ring revolution frequency.

  10. Additional Modules • GPS and GPS Interface Module • GPS provides time source and NTP time service to the site computers. • VME interface card captures the GPS time at each “Cycle Start” time. • Captured time is sent out on the RTDL. • Event Link Monitor • Monitors the event link and records which events occurred and when. • Buffers one full “Super-Cycle” (10 seconds). • Used by the event-link part of the time line monitor to make sure the event link is correct.

  11. Machine Cycle Timeline Time Critical Events, (soft events disabled) Informational Events, non critical timing Real-Time Data Link(RTDL) RTDL parameter transmission(for next cycle) RTDLTransmit MPS FPL RF & High Voltage Events Extract MPS FPAR (Alternate) Cycle Start End Injection Snapshot, 1Hz, 6Hz, etc… Beam On System xxx Trigger Events Cycle Start Extraction Kicker Charge RTDL Valid Event Link Mostly Stable Triggers Beam On Range beam accumulation Allowed Range for Variable Triggers Anytime Machine Anytime Line-Synch Reference Clock -60 Hz ZeroCrossing +60 Hz ZeroCrossing 0 2 ms 4 ms 5 ms 6 ms 1 ms 3 ms 7 ms 8 ms

  12. The Product and the Perpetrators

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