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This document provides a comprehensive overview of the SNS Timing System, detailing its components including the GPS-based time server, Eventlink architecture, and various VME modules. It discusses the hardware status of the system, highlighting the number of prototypes built and distributed to laboratories, and outlines the remaining work for system completion. Key features such as flexible triggering, prioritized events, and internal timestamp monitoring are covered, emphasizing the integration of advanced timing technology for optimizing performance in laboratory settings.
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SNS Timing System Overview Brian Oerter (BNL)
SNS Timing System Components • Line locked reference clock (LANL) • GPS based stratum 1 time server & interface to the Rtdl • Eventlink Master • VME eventlink slave module (V124s) • Fiber/electrical distribution • RealTimeDataLink Master • VME utility module (LANL) • Eventlink Monitor • Final design review held 7/31/01 at LANL
Time of Day • Navistar GPS satellite receiver • Network time server • Ethernet interface with NTP • IRIG “B” output • VME module w/IRIG input
Time of day IRIG “B” ETHERNET
Event Link System • Master • V123s VME encoder • V101 input module (16 channels) • 256 Events or triggers • 64 hardware • 192 software (FIFO) • Events Prioritized by position • Expandable
Event link System • V124s (slave) • Flexible triggering • Recovers RF clock (< 1 ns PP jitter) • Eight individually programmable channels • Delayed triggers • RF clock phase reset at start of cycle • Provides VME interrupts • imbedded interface (mps, instrumentation)
Real Time Data Link • Master • V105s encoder module • V106/206 input module • IRIG “B” receiver module • Operation • Master transmits 24 bit data frames • Up to 256 Frames (requires multiple chassis) • V105s contains a list of the frames to be transmitted
Real Time Data Link • Utility module • Receives Event link transmissions • Generates VME interrupts on selected events • Small FIFO avoids missed events • Receives RTDL transmissions • All received frames are stored in local memory • Monitors chassis voltage, fan status & air temp • Interrupts IOC on environment fault • Inputs for external interrupts to IOC • IOC reset via RTDL • Imbedded interface (mps, instrumentation)
Eventlink Monitor • Receives all events • Filter allows selective event storage • Internal timestamp counter • Events stored in memory with timestamp
Eventlink Monitor AGE 233321 -183312 AU3 249989 -166644 APP 266659 -149974 BSTR_PEAKER_0xB0 273924 -142709 TANDEM_10HZ 289521 -127112 B.F3_A5_TRIGGER 368571 -48062 TANDEM_10HZ 389521 -27112 AFR 399971 -16662 AT0 416633 0 SEB.F10_HS_STRT.RT 416634 1 AGT.END_CAL&JAM.RT 416643 10 AGN.MCR_TR_6.RT 416653 20 AGN.MCR_TR_7.RT 416681 48 AGN.MCR_TR_8.RT 416715 82 AGN.MCR_TR_5.RT 416723 90 AGN.MCR_TR_2.RT 416733 100 AGN.MCR_TR_1.RT 416735 102 AGN.MCR_TR_3.RT 416737 104 AGN.MCR_TR_4.RT 416739 106 EV-SPIN-UP 417783 1150
Hardware Status • Eventlink • Two VME chassis have been purchased and received • Six V123s prototypes built • Four distributed to member labs • Two additional modules sent to ORNL • 12 V101 built • Four distributed to member labs • Four installed in SNS master chassis • Four additional modules sent to ORNL
Hardware status (con’t) • V124s • Three prototypes built • One sent to ORNL • 10 pre-production modules on order • 50 more units to be built this year • Work remaining on Eventlink system • Submit V123s changes to drafting & build 2 production modules.
Hardware status (con’t) • RTDL System • GPS equipment has been received and installed • 8 V105s built • Four distributed to member labs • Four additional modules sent to ORNL • 12 V106s built • Eight distributed to member labs • Four additional modules sent to ORNL
Hardware status (con’t) • Work remaining on RTDL • V206 (8 channel) • Design in drafting • Build 16 production modules • Other work • Build/Test eventlink monitor • Complete design of 16 channel fanout • Built production fanouts