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Unit 1 Introduction to CO, Computer Evolution and Arithmetic

Unit 1 Introduction to CO, Computer Evolution and Arithmetic. Architecture & Organization 1. Architecture is those attributes visible to the programmer Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. e.g. Is there a multiply instruction?

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Unit 1 Introduction to CO, Computer Evolution and Arithmetic

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  1. Unit 1 Introduction to CO, Computer Evolution and Arithmetic

  2. Architecture & Organization 1 • Architecture is those attributes visible to the programmer • Instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques. • e.g. Is there a multiply instruction? • Organization is how features are implemented • Control signals, interfaces, memory technology. • e.g. Is there a hardware multiply unit or is it done by repeated addition?

  3. Architecture & Organization 2 • All Intel x86 family share the same basic architecture • The IBM System/370 family share the same basic architecture • This gives code compatibility • At least backwards • Organization differs between different versions

  4. Structure & Function • Structure is the way in which components relate to each other • Function is the operation of individual components as part of the structure

  5. Function • All computer functions are: • Data processing • Data storage • Data movement • Control

  6. Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Functional view • Functional view of a computer

  7. Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operations (1) • Data movement • e.g. keyboard to screen

  8. Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operations (2) • Storage • e.g. Internet download to disk

  9. Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operation (3) • Processing from/to storage • e.g. updating bank statement

  10. Data Storage Facility Data Movement Apparatus Control Mechanism Data Processing Facility Operation (4) • Processing from storage to I/O • e.g. printing a bank statement

  11. Structure - Top Level Computer Peripherals Central Processing Unit Main Memory Computer Systems Interconnection Input Output Communication lines

  12. Structure - The CPU CPU Arithmetic and Login Unit Computer Registers I/O System Bus CPU Internal CPU Interconnection Memory Control Unit

  13. Structure - The Control Unit Control Unit CPU Sequencing Login ALU Control Unit Internal Bus Control Unit Registers and Decoders Registers Control Memory

  14. Evolution of Computer 1 • Zeroth Generation : Mechanical Era (1600-1940) • Wilhelm Schickhard (1623) • Blaise Pascal (1642) • Von Leibniz (1646-1716) • Babbage’s Differential Engine (1822-36) • Babbage’s Analytical Engine • George Boole (1847) • Herman Hollerith (1880) – Punched Cards • KonradZuse (1938):Automatic Calculating Machine based on Electromagnetic mechanism • Howard Aiken (1943) : Mark1 (72 words of 23 decimal digit)

  15. Evolution of Computer 2 • First Generation : Vacuum Tubes (1946-1957) • ENIAC ( Electronic Numerical Integrator and Calculator) • Started in 1943 • For preparing trajectory tables of weapons. • John Mauchly and John Eckert in University of Pennsylvania • 30 tones, 15,000 square feet, 18,000 tubes, 140 KW • 5000 addition/sec, Decimal, 20 Accumulators • Programming by Plugging and Unplugging of switches • Results were punched on cards or printed on type writer. • Completed in 1946

  16. Evolution of Computer 3 • First Generation (contd.) • Stored Program Concept • EDVAC ( Electronic Discrete Variable Computer) • The Von-Neuman Machine (IAS Computer) Arithmetic and Logic Unit Input Output Equipment Main Memory Program Control Unit

  17. Evolution of Computer 4 • First Generation ( Von-Neuman Machine contd..) • 1000 x 40 bit words memory • Binary number • 2 x 20 bit instructions Ref: Computer Organization and Architecture by William Stallings

  18. Evolution of Computer 5 • Detailed Von Neuman Architecture Central Processing Unit Arithmetic and Logic Unit Accumulator MQ Arithmetic & Logic Circuits MBR Input Output Equipment Instructions & Data Main Memory PC IBR MAR IR Control Circuits Address Program Control Unit

  19. Evolution of Computer 6 • Von Neuman Instruction • Supports 21 different instruction. Ref: Computer Organization and Architecture by William Stallings

  20. Evolution of Computer 8

  21. Evolution of Computer 9 • 1947 - Eckert-Mauchly Computer Corporation • UNIVAC I (Universal Automatic Computer) for US Bureau of Census 1950 calculations • Late 1950s - UNIVAC II • Faster • More memory • Birth of IBM and Sperry in 1950s. • 1953-IBM 701 for scientific calculations • 1955-IBM 702 for Business Application

  22. Evolution of Computer 10 • Second Generation (1955-1965) -Transistors • Transistor Replaced vacuum tubes • Smaller, Cheaper, Less heat dissipation, Solid State device, Made from Silicon (Sand),Invented 1947 at Bell La • Multiplexor, Data Channel • Concept of System Software • PDP-1,IBM 7094 with instruction backup register

  23. Evolution of Computer 11 • Third Generation (1965-1971) • Concept of Small Scale Integration • IBM System 360 • PDP-8 from DEC • Semiconductor based memory

  24. Evolution of Computer 12 • Later Generation • LSI,VLSI • 1971 – 4004 : • Developed by Intel • First microprocessor • All CPU components on a single chip • 4 bit • Followed in 1972 by 8008 • 8 bit • Both designed for specific applications • 1974 - 8080 • Intel’s first general purpose microprocessor

  25. Pentium Evolution 1 • 80486 • sophisticated powerful cache and instruction pipelining • built in maths co-processor • Pentium • Superscalar • Multiple instructions executed in parallel • Pentium Pro • Increased superscalar organization • Aggressive register renaming • branch prediction • data flow analysis • speculative execution

  26. Pentium Evolution 2 • Pentium II • MMX technology • graphics, video & audio processing • Pentium III • Additional floating point instructions for 3D graphics • Pentium 4 • Note Arabic rather than Roman numerals • Further floating point and multimedia enhancements • Itanium • 64 bit

  27. Designing for Performance • Execution Time, Response Time, Throughput • Processor Speed: Clock Rate, Memory System, Instruction Architecture and Pipelining • Design of Hardware • How to improve Performance ? • T=N*S/R, where T=Processor Time, N= Size of Machine Language Instruction, S=Average no of basic steps for execution, R=Clock Rate • MIPS Rate=(1/average time for execution of inst.) * 106 • MFLOPS

  28. Computer Components • Central Processing Unit • Memory Unit • Input and Output Unit • Interconnection Unit/Interfaces • Software

  29. Bus Interconnection • Bus • A communication pathway connecting two or more devices • A number of channels in one bus • e.g. 32 bit data bus is 32 separate single bit channels

  30. Classification of Buses in detail • Data Bus • Carries data • Width of bus is a key determinant of performance • Address Bus • Identify the source or destination of data • Bus width determines maximum memory capacity of system e.g. 16 bit address bus giving 64k address space • Control Bus • Control and timing information • Memory read/write signal • Interrupt request • Clock signals

  31. Types of Bus Structure • Single Bus Structure Memory Memory Input Output Processor • Lots of devices on one bus leads to: Propagation delays • Solution on that to use multiple buses

  32. Types of Bus Structure • Multi-Bus Structure

  33. Interconnection Networks • Time Shared Bus/Common Bus Memory I/O Processor I/O Memory Processor

  34. Interconnection Networks • Multiprocessor with unidirectional buses Control Logic Processor I/O Processor Memory Module I/O devices Bus Modifier

  35. Interconnection Networks • Multi-Bus Multiprocessor Organization I/O Processor Memory Module Processor Memory Module Memory Module Processor Processor I/O Processor

  36. Interconnection Network • Crossbar switch M0 M1 M m-1 P0 I/O0 P p-1 I/O c-1

  37. Floating Point Addition and Subtraction

  38. Floating Point Multiplication

  39. Floating Point Division

  40. Syllabus (No. of lectures allotted : 8 Hrs) • A Brief History of computers • Von Neumann Architecture • Harvard architecture • Bus Interconnection • Scalar Data Types • Fixed and Floating point numbers • Booths algorithm for multiplication and its Hardware Implementation • Division: Restoring and Non Restoring algorithms • IEEE standards of Floating point representations • Floating point arithmetic. Unit I : Computer Evolution and Arithmetic

  41. Teaching Plan Unit I : Computer Evolution and Arithmetic

  42. Historic Events • 1623, 1642: Wilhelm Strickland/Blaise Pascal built a mechanical counter with carry. • 1823-34: Charles Babbage built the difference engine. • 1943-44: John Mauchly (professor) and J. Presper Eckert (graduate student) built ENIAC (Electronic Numerical Integrator and Computer) at U. Penn. • 1944: Howard Aiken used “separate data and program memories” in MARK I computer – Harvard Architecture. • 1945-52: John von Neumann proposed a “stored program computer” EDVAC (Electronic Discrete Variable Computer) – Von Neumann Architecture – use the same memory for program and data. Unit I : Computer Evolution and Arithmetic

  43. ENIAC - background • Electronic Numerical Integrator And Computer • Eckert and Mauchly • University of Pennsylvania • Trajectory tables for weapons • Started 1943 • Finished 1946 • Too late for war effort • Used until 1955 Unit I : Computer Evolution and Arithmetic

  44. ENIAC - details • Decimal (not binary) • 20 accumulators of 10 digits • Programmed manually by switches • 18,000 vacuum tubes • 30 tons • 15,000 square feet • 140 kW power consumption • 5,000 additions per second Unit I : Computer Evolution and Arithmetic

  45. Von Neumann/Turing • Stored Program concept • Main memory storing programs and data • ALU operating on binary data • Control unit interpreting instructions from memory and executing • Input and output equipment operated by control unit • Princeton Institute for Advanced Studies • IAS • Completed 1952 Unit I : Computer Evolution and Arithmetic

  46. Structure of Von Neumann machine Unit I : Computer Evolution and Arithmetic

  47. IAS - details • 1000 x 40 bit words • Binary number • 2 x 20 bit instructions. • Each no. Represented by a sign bit & a 39 bit value • OR a word may also contain 2, 20 bit instructions. Where 8 bit specifies op-code & remaining 12 bits for address of one of the word in memory Unit I : Computer Evolution and Arithmetic

  48. Set of registers (storage in CPU): • Memory Buffer Register: Contains a word to be stored in memory or is used to receive a word from memory • Memory Address Register: specifies the address in memory of the word to be written from or read into the MBR • Instruction Register: contains the 8 bit op-code of instruction being executed • Instruction Buffer Register: employed to temporarily hold the right hand instruction from a word in memory Unit I : Computer Evolution and Arithmetic

  49. Program Counter: contains the address of the next instruction pair to be fetched from memory • Accumulator & Multiplier Quotient: employed to temporarily hold operands and results of ALU operations. The result of multiplying 2, 40 bit nos. is an 80 bit no., the most significant 40 bits are stored in the AC & the least significant in the MQ. Unit I : Computer Evolution and Arithmetic

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