BUS INTERFACE • Buses are collection of wires that carries information. • Bus system are located within the PC for interfacing different types of I/O even memory in some cases. • ISA (industry standard Architecture ) • 8bit ISA bus • Adress (A0~A19) • Data line(D0~D7) • Four control Signals
Continued… • Other signals: • IRQ2~IRQ7 • DRQ1~DRQ3 • DACK0~DACK3 • Power • Reset
16 bit ISA BUS • An additional connector is attached (18+18) 36pins to accommodate: • D8~D15 • A20~A23 • IRQ10~IRQ14 • DRQ0,DRQ5~DRQ7 • DACK0,DACK5~DACK7 • some control signals
EISA BUS • Extened ISA 32 bit • 38 pins: • D16 ~D31 • Other necessary control were added • Speed(still 8 MHZ) • Pin Space
VESA Local Bus • The Video Electronics Standards Association or VESA designed the bus originally so the personal computer could communicate at a higher rate of speed than offered by the ISA bus. • Extension of ISA Bus • Speed • Common for Video retrieval devices and Disk Interface
PCI BUS • The only bus available in newest P4 and other computer system. • VESA Local Bus • 32 & 64 bit data sizes • Speed • Plug and Play characteristics • Multiplexed
Continued… • 32 bit cards have 124 pins • 64 bit cards have 188 pins • Memory • Microprocessor • Configuration Memory • Extension of System BIOS
PCI Command • 0000 Interrupt Acknowledge • This is a special form of read cycle implicitly addressed to the interrupt controller. • 0001 Special Cycle • Special cycle is used to transfer the data to all PCI components. • 0010 I/O Read • This performs a read from I/O space.
Continued… • 0011 I/O Write This performs a write to I/O space. 0100-0101 Reserved A PCI device must not respond to an address cycle with these command codes. 0110 Memory Read This performs a read cycle from memory space.
Continued…. 0111 Memory Write This operates similarly to a memory read. 1000-1001 Reserved A PCI device must not respond to an address cycle with these command codes. 1010 Configuration Read This is similar to an I/O read, but reads from PCI configuration space.
Continued… • 1011 Configuration Write This operates analogously to a configuration read. 1100 Memory Read Multiple This is similar to memory read access, except that it is usually used many data instead of one. 1101 Dual Address Cycle When accessing a memory address that requires more than 32 bits to represent
Continued… • 1110 Memory Read Line Used to read more than two 32 bit numbers from PCI bus. • 1111 Memory Write and Invalidate This is same as line memory access ,but it is used with write.
Universal Serial Bus • An ideal interface for devices like key board, video retrieval,modem etc. • 127 connection • Data transfer rate • Cable length • Maximum power(overload) • Better soln
USB Connectors • There are two types of 4 pins connectors
Continued • Pin 1 +5v • Pin 2 –data • Pin 3 +data • Pin 4 Gnd • Data signals are biphased. • Actual data transmitted includes sync bits, a method called bit stuffing, because it lengthens the data stream.
Continued… • If logic 1 is transmitted for more than 6 bits in a row, the bit stuffing technique adds an extra bit (logic 0) after six continuous 1s in a row. • data is always transmitted with the least-significant bit first, followed by subsequent bits • USB use NRZI encoding for transmitting packet.
USB COMMANDS • To begin communication, sync byte 80H is transmitted first, followed by the packet identification byte (PID). • The PID contains 8 bits. –only the rightmost 4 bits contain the type of packet that follows, if any • The leftmost 4 bits of the PID are the ones complementing the rightmost 4 bits.
CONTINUED…. • in the token packet, the ADDR (address field) contains the 7-bit address of the USB device • –up to 127 devices present on at a time • ENDP (endpoint) is a 4-bit number used by the USB. • Endpoint 0000 is used for initialization • –other endpoints are unique to each USB device
Continued… • Two types of CRC (cyclic redundancy checks) used on USB. • 5-bit CRC generated with polynomial X5+ X2+ 1 • –a 16-bit CRC, used for data packets, generated with the X16+ X15+ X2+ 1 polynomial •When using 5-bit CRC, a residual of 01100is received for no error in all five bits of the CRC and the data bits. • 16-bit no error CRC residual is 1000000000001101
stop and wait flow control • Once a packet is transferred from host to USB device, if data & CRC are received correctly, ACK (acknowledge) is sent to the host. • If data and CRC are notreceived correctly, the NAK (not acknowledge) is sent. • –if the host receives a NAK token, it retransmitsthe data packet until it is received correctly • This method of data transfer is often called stop and wait flow control.
Continued… • host must wait for client to send an ACK orNAK before transferring additional data packets
AGP • Operate at bus clock frequency of the microprocessor • Used for video cards and system memory only • Can transfer data up 528 Mbytes per sec