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Contents. 5 CMOS Logic Basics(1)- combinational logic. 1. Dynamic NMOS logic 2. Pseudo NMOS logic Transistor sizing Complex logic gate layout 3. Static(complementary) CMOS logic Inverter, NAND, NOR gates layout 4. Pass transistor logic 5. BiCMOS logic 6. Dynamic CMOS logic.

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## 5 CMOS Logic Basics(1)- combinational logic

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**Contents**5 CMOS Logic Basics(1)-combinational logic 1. Dynamic NMOS logic 2. Pseudo NMOS logic • Transistor sizing • Complex logic gate layout 3. Static(complementary) CMOS logic • Inverter, NAND, NOR gates layout 4. Pass transistor logic 5. BiCMOS logic 6. Dynamic CMOS logic**1. Dynamic NMOS Circuits**Q. Why we study dynamic NMOS which is not popular ? (compared to CMOS) A. Simple vehicle for understanding dynamic operation. PMOS Static +area, +speed +power +area (utilize para. C) NMOS Static NMOS Dynamic +power -area -speed CMOS Static CMOS Dynamic +area +speed**VDD**i) 2 phase, ratioed type 2 1 2 1 2 Vi C2 C3 C1 1 2 Low level is determined from inverter ratio demands large chip area! Vi VC1 VC2 VC3**C3**DV = VDD : Charge sharing between C2 and C3 C2+C3 VDD ii) 2 phase, ratioless A f1 f2 Vi C2 C1 C4 C3 f1 f2 Vi VC1 Ta Tb Ta: DC power consmption due to ratioed operation Tb: ratioless operation VC2 DV VL VC3 VC4 VL O**iii) 2 phase ratioless B**• Vi가 high이고 1이 on 일때 VDD-GND DC경로를 표 한 T1이 차단 • Charge Sharing에 의한 전압강하 • C기생성분의 증가로 CV2f(dynamic 전력소모) 증가 VDD f1 f2 C2 T1 Vi C1 C3 C4**iv) 2 phase ratioless C**f1 f2 • No DC path • extremely large CV2f dissipation and large clock driver • simple layout Vi f1 f2**v) 4 phase ratioless A**f1 f2 f3 f4 f2 f3 f4 f1 f1 f2 f3 f4 f1 f2 f3 f4 Type 2 Type 3 Type 4 Type 1 Type 1 2 3 4 E P H H H E P H H H E P P H H E f1 f2 E : evaluate P : precharge H : hold f3 f4**1**2 1 2 2 3 12 23 x y 1 2 1 2 vi) 4 phase ratioless B T1 장 * same as 5. except T1 which prevents charge sharing between x and y improves noise immunity**2. Pseudo NMOS logic**• A kind of ratioed logic as R-load, depletion-load. • No body effect grounded-gate PMOS is close to constant current source load VDD pseudo NMOS const. I src IL IL depl. Vo R PDN enh. Load line curve Vo VOL is given by**Pseudo-NMOS vs. Complementary CMOS**• (Pros.) of Pseudo -NMOS 1. Smaller number of transistors less area, less capacitive loading to preceding gate • (Cons.) 1. Power consumption due to DC current path: low NML( i.e., high low-output VOL=ILRPDN) • (Comments) Pseudo-NMOS is desirable for applications where speed is of major importance, or where we know that the majority of outputs are high, such as address decoder in memory**Design constraints of pseudo-NMOS**1. Power consumption : to reduce static power 2. noise margin: to obtain reasonably high NML, VOL=ILRPDN should be low. 3. output rise time 4. output fall time RPU large 1. Power consumption 2. Noise margin RPDN small 3. Rise time 4. Fall time RPU small : contradictory**VDD**Ceff • Answer to Question Q1. How do we consider capacitance to VDD ? A1. Capacitance to VDD and all other DC nodes are lumped as capacitance to ground. Charge variation on node x due to = = = x**Q2. Name a circuit where capacitance ratio, not value,**determines the behaviour. A2. Switched-capacitor filter i V1 V2 V1 V2 i f f C2 C1 capacitance-ratio**Variations of pseudo-NMOS**i) parallel large adaptive PMOS load In pseudo-NMOS tPLH is quite large to make VOL low enough(i.e., NML high enough). In standby, large PMOS pull-up, M1 is off, which is turned on after an address translation is detected to result in large current drive.**Ex.) Pseudo-NMOS layout example(4-input NAND)**(W/L)NMOS = 1.8/1.2 (W/L)PMOS = 1.8/4.8**Istatic = 48.5A, VOH = 5V, VOL = 0.48V**VM = 1.62V, NMH = 3.26V, NML= 0.27V tpHL = 0.6nsec, tpLH = 2.37nsec Trying to make PMOS longer to increase NML yields even worse tpLH, which is already large. If we change to (W/L)NMOS = 7.2/1.2, (W/L)PMOS = 1.8/1.2, Istatic 0.18mA, tpHL 0.24ns, tpLH 1.4ns**I**Q I i Q p n n p i ii) CMOS Multi-drain Logic • This idea came from I2L(Integrated-Injection Logic). • Low energy due to low switching voltage • NOR-type logic only**Z=A+B**A B Q. Why is I2L not used much ? A. 1) efficiency of PNP current source 2) CMOS is better in area, power, speed**A**Z=A+B B A+B • Fanout limited by NML**A**B C Z iii) Ganged CMOS logic • NOR gate ; Z = A+B+C • Can be operated as NAND gate by suitably ratioing PMOS over NMOS. • Can be operated as quarternary logic**Q**Q Q Q a a b b ... ... c iv) Cascode Logic(1) : CVSL • CVSL(Cascode Voltage Switch Logic) or DCVSL(Differential Cascode Voltage Switch Logic) • CVSL : requires dual signal rail ratioed logic(DC path exists) large current spike during switching regenerative feedback fast(?)**SSDL(Sample-Set Differential Logic) : modified version of**dynamic CVSL • during clk low (sample) ; one at VDD, the other at slightly below VDD • during clk high (set) : set to VDD & VSS quickly**out**out VX VR in in v) Cascode Logic(II) : DSLL(Differential Split Level Logic) • replaces p-load in pseudo-NMOS with cross-coupled cascoded NMOS and PMOS set when when PMOS, NMOS의 size를 이 조건에 맞도록 정한다.**t1**t3 P1 n1 P3 in out C1 n2 in P2 P4 out t2 C2 VR VR • in : low(0V), in : high 일때 P2 is fully ON, A is pulled to VDD, C2 is discharged P1 is not fully OFF, A is at 0.5-0.6V(just below VTN of n1) C1 is charged to via t3, P3 • Switch in to and in to 0V. P1 turns on very fast( it wasn’t completely OFF) t2 turns on very fast( it was just under threshold) A VDD, A 0.5-0.6V **Size of PMOS is set indep. of pull-down NMOS, as they are**decoupled by cascode NMOS. Therefore, charging through PMOS is faster than in pseudo-NMOS. • Repartitioning the gate to open-drain structure, where input and output resides in(0, ), thus improving speed. ( Voltage swing in large C is reduced.) Interconnection line is inserted here **iv) SPFL(Source Follower Pull-up Logic)**• extensive use of NMOS over slower PMOS • utilizing parallel connection instead of slower series connection good for NOR gate • P1 is turned off if anyone of N1-N4, connected as parallel source follower, is turned on • suffers from body effect and degraded VH in the internal node(Nload).**3. Static(Complementary) CMOS**• inverter layout • PMOS drain(p-diffusion) and NMOS drain(n-diffusion) can be connected via metal strap and contacts. • Power and ground are run in metal and connected to the sources of PMOS & NMOS.**Static CMOS NAND gate**• default in standard cell layout : horizontal PWR, GND/vertical poly-silicon gate (to make the height of cells constant regardless of functionality)**Static CMOS NOR gate**• (b) is faster than (a) Why ?**Delay(ns) (before/after sizing)**area(before/after sizing) • Transistor sizing for 8-input NAND gate Appr. 1 2.82 + 3.37 = 6.2 4.6 216 120 Appr. 2 0.88 + 4.36 = 5.24 4.8 216 136 Appr. 3 0.31+0.4+0.31+2.17=3.193.5 360 124**VDD**f • Complex gate layout i) Linear Array • Think of an AOI(And-OR-Invert) cell : f = 1 2 f 3 4 5 In static CMOS circuit**P-MOS**poly-Si N-MOS a a’ active area aluminum contact N N P-well • Since each P-N pair(sharing the same input) is represented by Symbolize by**1**2 3 4 5 VDD VDD 1 2 3 out 4 5 3 5 VSS 1 2 4 VSS • Symbolic Layout of AOI gate (Layout ‘a’) Noting that**1**2 3 4 5 VDD VDD P N 1 out 2 3 VSS out 4 5 VSS out VDD out VSS 1 3 2 4 5 • Layout ‘a’ can be simplified • If we interchange 2 and 3 (Layout ‘b’) Observation : 1-3-2-4-5 is and Euler path for N-graph. But not for P-graph. Ques. How to find a sequence which is an Euler path for both P-and N-graph. (Layout ‘c’)**2**3 out 1 4 5 VDD 2 3 1 4 5 VDD 3 2 out VSS out 1 4 5 VSS VDD 2 3 Ans. Sequence 2-3-1-4-5- is it! Ques. How do we find it consistently? 1 4 5 out 3 5 1 2 4 (a) (b) VSS P-part N-part (Layout ‘d’)**2**3 1 4 5 2 3 • Euler path methold 1 4 5 2 3 1 4 5 Stretch 2 3 2 3 2 3 1 1 Split contact 4 5 4 5 4 5 (rubber band)**1. Find all Euler paths that cover the graph.**2. Find a p- and an n-Euler path that have identical labeling(a labeling is an ordering of the gate labels on each vertex). 3. If the paths in step 2 are not found, then break the gate in the minimum number of places to achieve step 2 by separate Euler paths.**관찰 1) Euler path가 존재하면 그 path에 포함된**모든 edge에 대응하는 gate는 diffusion 영역을 공유하면서 연결된다. 관찰 2) 전체 edge를 지나는 Euler path가 존재하지 않으면 전체 graph를 Euler path를 갖는 subgraph로 분할한다.(여기서 모든 Euler path는 p-와 N-graph 모두에게 존재하는 것을 뜻한다.) 이때, 각 subgraph는 layout에서 각 diffusion island(혹은, interlace)를 형성하고, 각 interlace 사이에는 gap이 있다. 관찰 3) Reduction of graph ; 홀수개의 edge로 된 series, 혹은 parallel graph는 single edge로 줄여서 Euler path를 찾은 후, 원래 graph 상의 Euler path로 복원시킬 수 있다. 관찰 4) make the # of inputs to all gates to be odd, by inserting dummy input, so that E-graph can always be found.**1**2 3 8 4 10 5 6 9 7 • Graph reduction fro finding Euler path (복원 2) (복원 1) (축약 2) (축약 1) , example.**reduction phase**• Graph model (축약 2) (축약 1) E-path reconstruction 1 1 10 3 (복원 1) 2 4 (복원 2) 8 5 7 9 6**P1**2 8 3 1 10 4 5 9 P2 ex. 1 P1 2 • Appending pseudo input • Heuristic algorithm ; 1. Add pseudo-input to every gate with an even number of inputs. 2. Rearrange the input sequence such that # of interlaces between real and pseudo inputs is minimal. Top and bottom pseudo inputs does not contribute to separation areas. 8 P1, P2 : pseudo input 3 10 P2 4 9 5 3 2 P1 1 4 5 P2**Minimal Interlace Algorithm**White ; pseudo input Black ; real input White & Black ; gate with bothpseudo and real input**When a signal is applied to multiple transistors.**ex) CMOS XNOR gate 2-NAND NMOS PMOS**Gate Matrix layout algorithm**• Transistors are grouped in strips to allow maximum source/drain connection by abutment. To achieve better grouping, polysilicon columns are allowed to interchange to increase abutment. • The resultant groups are then placed in rows with groups maximally connected to the VSS and VDD rails placed toward these signals. Row placement is then based on the density of other connections. • Routing is achieved by vertical diffusion or Manhattan(horizontal and vertical) metal routing. This normally would require a maze router.

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