EE3541 Introduction to Microprocessors

1. EE3541 Introduction to Microprocessors Hardware Detail of Intel 8086 Medien Zeghid EE Department PRINCE SATTAM BIN ABDULAZIZ UNIVERSITY COLEGE OF ENGINEERING AT WADI ADDAWASER

2. 8086 Pin Configuration

3. 8086 Pin Description Pin Name Pin Number Description Direction GND: 1 & 20 Both need to be connected to ground

4. 8086 Pin Description Pin Name Pin Number Description Direction VCC: 40 VCC = 5V

5. 8086 Pin Description Pin Name Pin Number Description Direction CLK: 19 Input 33% duty cycle 2/3*T 1/3*T

6. 8086 Pin Description Pin Name Pin Number Description Direction RESET: 21 Input Reset 8086 • Duration of logic high must be greater than 4*T • After reset, 8088 fetches instructions starting from memory address FFFF0H

7. 8086 READY Selected memoryor I/O device READY Data bus wait for memoryor I/O ready Start data transfer 8086 Pin Description Pin Name Pin Number Description Direction READY 22 Input Informs the processor that the selected memory or I/O device is ready for a data transfer

8. 8086 Pin Description Pin Name Pin Number Description Direction MN/MX: 33 Input High  Minimum mode Low  Maximum mode The 8086 microprocessor can work in two modes of operations : Minimum mode and Maximum mode. In the minimum mode of operation the microprocessor do not associate with any co-processors and can not be used for multiprocessor systems. In the maximum mode the 8086 can work in multi-processor or co-processor configuration. Minimum or maximum mode operations are decided by the pin MN/ MX(Active low).

9. HOLD 8086 Device 2 HLDA Bus Memory 8086 Pin Description Pin Name Pin Number Description Direction HOLD 31 Input The execution of the processor is suspended as long as HOLD is high HLDA 30 Output Acknowledges that the processor is suspended • Procedure for Device 2 to use bus • Drive the HOLD signal of 8086 high • Wait for the HLDA signal of 8086 becoming high • Now, Device2 can send data to bus

10. INTR INTR 8086 INTA External device INTA Data Bus Int. type Data bus 8086 Pin Description Pin Name Pin Number Description Direction NMI 17 Input Causes a non-maskable type-2 interrupt INTR 18 Input Indicates a maskable interrupt request INTA 24 Output Indicates that the processor has received anINTR request and is beginning interruptprocessing • NMI (non-maskable interrupt): a rising edge on NMI causes a type-2 interrupt • INTR: logic high on INTR poses an interrupt request. However, this request can be masked by IF (Interrupt enable Flag). The type of interrupt caused by INTR is read from data bus • INTA: control when the interrupt type should be loaded onto the data bus

11. D Q G 8086 Pin Description Pin Name Pin Number Description Direction ALE 25 Output Indicates the current data on 8086 address/data bus are address A[19:8] Buffer A[19:8] ATE 8086 A[7:0] AD[7:0] D latches D[7:0]

12. 8086 Pin Description Pin Name Pin Number Description Direction DEN 26 Output Disconnects data bus connection DT / R 27 Output Indicates the direction of data transfer DEN DT/R 1 X Disconnected 0 0 To 8088 0 1 From 8088 DEN 8086 DT/R D[7:0] Data bus DEN DT/ R AD[7:0]

13. 8086 Pin Description Pin Name Pin Number Description Direction WR 29 Output Indicates that the processor is writing to memory or I/O devices RD 32 Output Indicates that the processor is reading from memory or I/O devices IO/ M 28 Output Indicates that the processor is accessing whethermemory (IO/M=0) or I/O devices (IO/M=1) WE WR or RD WR OE I/O RD Addr. Dec. CS Addr. Dec. Memory IO/M IO/M 8086

14. 8086 Pin Description AD0-AD15 (Bidirectional) Address/Data bus Low order address bus; these are multiplexed with data. When AD lines are used to transmit memory address the symbol A is used instead of AD, for example A0-A15. When data are transmitted over AD lines the symbol D is used in place of AD, for example D0-D7, D8-D15 or D0-D15. A16/S3, A17/S4, A18/S5, A19/S6 High order address bus. These are multiplexed with status signals

15. 8086 Pin Description

16. 8086 Pin Description

17. 8284 Clock Generator 8284 8086 RDY1 Ready1 Ready2 RDY2 Ready Ready X1 510 CLK CLK X2 510 +5V RESET RESET RES 100K • Generates 33% duty cycle clock signal • Generates RESET signal • Synchronizes ready signals from memory and I/O devices 10uF

18. System Timing Diagrams • T-State: • One clock period is referred to as a T-State T-State • An operation takes an integer number of T-States • CPU Bus Cycle: • A bus cycle consists of 4 or more T-States T1 T2 T3 T4

19. Memory Read Timing Diagrams T3 T4 T2 T1 CLK A[15:8] ALE Buffer A[15:0] 8086 A[19:16] A[19:16] S3-S6 AD[7:0] A[15:0] A[15:0] D latch Memory AD[7:0] A[7:0] D[7:0] IO/M D[7:0] Trans -ceiver DT/R DT/R DEN DEN IO/M RD WR RD WR

20. Memory Write Timing Diagrams T3 T4 T2 T1 CLK A[15:8] ALE Buffer A[15:0] 8086 A[19:16] A[19:16] S3-S6 AD[7:0] A[15:0] A[15:0] D latch Memory AD[7:0] A[7:0] D[7:0] IO/M D[7:0] Trans -ceiver DT/R DT/R DEN DEN IO/M RD WR RD WR

21. INTR 8086 External device INTA Data bus Interrupt Acknowledge Timing Diagrams T3 T4 T2 T1 CLK ••• INTR ••• INTA D[7:0] ••• Int. Type • It takes one bus cycle to perform an interrupt acknowledge • During T1, the process tri-states the address bus • During T2, INTA is pulled low and remains low until it becomes inactive in T4 • The interrupting devices places an 8-bit interrupt type during INTA is active

22. HOLD 8086 Device 2 HLDA Bus Memory HOLD/HLDA Timing Diagrams T2 T3 T4 CLK ••• HOLD ••• HLDA Hold State • The processor will examine HOLD signal at every rising clock edge • If HOLD=1, the processor will pull HLDA high at the end of T4 state (end of the execution of the current instruction) and suspend its normal operation • If HOLD=0, the processor will pull down HLDA at the falling clock edge and resume its normal operation