Introduction to Microprocessors

1. Introduction to Microprocessors

2. AGENDA • Architecture • Microprocessor Communication and Bus Timings • Demultiplexing Address and Data Lines

3. Architecture of 8085 • Reveals the internal logic of a Microprocessor • 8085 Architecture consists of following blocks: • ALU logic • Register Logic • Timing and Execution Logic • Interrupt Logic • Serial I/O Logic

4. S Z X AC X P X C Flag Register Carry Sign Zero Parity Auxiliary Carry X - Unspecified

5. Register Section • General Purpose Registers • A, B, C, D, E, H, and L • BC, DE, and HL • Special Function Registers • Program Counter • Stack Pointer

6. Timing and Execution Logic Instruction Register Instruction Decoder Timing and Control Unit Control Signals

7. Interrupt Logic • Consists of 5 interrupts with following properties: • Priority • Maskable and Non Maskable • Vectored and Non – Vectored • INTA is an output signal

8. Serial I/O Logic • Supports serial I/O using 2 lines • SID – Serial Input Data • SOD – Serial Output Data

9. Mp communication and Bus Timings - 1 • The instruction code 0100 1111 (4FH – MOV C, A) is stored in memory location 2005H. Illustrate the steps and the timing of data flow when it is being fetched

10. RD Mp Communication And Bus Timings - 2 Data Bus 4F Internal Data Bus Memory 2000 B C Instruction Decoder D E ALU 2005 2005 4F H L SP PC Address Bus 4F Control Logic

11. Timing Diagram

12. Demultiplexing Address & Data Lines

13. Probable Questions.. • Explain with a neat diagram, the architecture of 8085 microprocessor • Explain the flag register of 8085. • With a neat diagram, explain how to separate multiplexed address and data lines in 8085. • Explain opcode fetch machine cycle. • What Signals are activated when I/O port at address ABCD H is read by 8085 ?