1. Assignment 8 solutions • 1) Design and draw combinational logic to perform multiplication of two 2-bit numbers (i.e. each 0 to 3) producing a 4-bit result (hint: use a separate Karnaugh map for each output bit) First column of 4-bit result: CD AB F=A.B.C.D Others give: F=AB’C+ACD’ F=A’BC+BCD’+AC’D+AB’D F=BD

2. Assignment 8 solutions

3. Assignment 9 solutions Design a 3-bit binary up-counter using D-FF to cycle over all odd numbers. To optimize the design, you are allowed to reset any even number states into any one of these odd numbers. At the end, show the complete state diagram with even numbered states, indicating which odd number they reset to. (Hint – your final design should contain 3 D-type flipflops and a single combinational logic gate)

4. Assignment 9 solutions Design a 3-bit binary up-counter using D-FF to cycle over all odd numbers. To optimize the design, you are allowed to reset any even number states into any one of these odd numbers. At the end, show the complete state diagram with even numbered states, indicating which odd number they reset to. (Hint – your final design should contain 3 D-type flipflops and a single combinational logic gate)

5. Assignment 9 solutions Design a 2 bit counter counting 0, 1, 2 using D-FF. There are two inputs: a data input which receives clock pulses, and a count direction input which when HIGH causes counting up and when LOW causes counting down. You may treat the excluded state 3 as you see fit to simply your design. At the end, indicate where the state 3 goes into

6. 1 0 1 0 0 Assignment 9 solutions Design a 2 bit counter counting 0, 1, 2 using D-FF. There are two inputs: a data input which receives clock pulses, and a count direction input which when HIGH causes counting up and when LOW causes counting down. You may treat the excluded state 3 as you see fit to simply your design. At the end, indicate where the state 3 goes into

7. A B Count Assignment 9 solutions Design a 2 bit counter counting 0, 1, 2 using D-FF. There are two inputs: a data input which receives clock pulses, and a count direction input which when HIGH causes counting up and when LOW causes counting down. You may treat the excluded state 3 as you see fit to simply your design. At the end, indicate where the state 3 goes into