1 / 22

Instruction Set Architectures

Instruction Set Architectures. Early trend was to add more and more instructions to new CPUs to do elaborate operations VAX architecture had an instruction to multiply polynomials! RISC philosophy ( Cocke IBM, Patterson, Hennessy, 1980s): Reduced Instruction Set Computing

dino
Télécharger la présentation

Instruction Set Architectures

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Instruction Set Architectures • Early trend was to add more and more instructions to new CPUs to do elaborate operations • VAX architecture had an instruction to multiply polynomials! • RISC philosophy (Cocke IBM, Patterson, Hennessy, 1980s): Reduced Instruction Set Computing • Keep the instruction set small and simple, makes it easier to build fast hardware. • Let software (compiler) do complicated operations by composing simpler ones. • ARM is RISC

  2. Chapter 2: The Programmer’s Model • Concerned with the features that are available to you from a high level, e.g. • Where data can be stored • What happens when the machine is given an invalid instruction Data Types: • Byte: 8 bits • Halfword: 16 bits • Word: 32 bits

  3. Processor Modes ARM has seven basic operating modes: • User: unprivileged mode under which most tasks run has limited access to the hardware (non-privileged) whereas all other modes have full access (privileged) to the CPU resources. • FIQ: entered when a high priority (fast) interrupt is raised • IRQ: entered when a low priority (normal) interrupt is raised • Super: entered on reset and execution of software interrupt instruction • Abort: used to handle memory access violations • Undef: used to handle undefined instructions • System: privileged mode using the same registers as user mode

  4. Processor Modes • We will mainly use User mode. Other modes much less important for this class. • For now, only concerned with r0-r12; treat these as registers that can be used to store any variable.

  5. ARM Registers Register – internal CPU hardware device that stores binary data; can be accessed much more rapidly than a location in RAM ARM has 13 general-purpose registers R0-R12 1 Stack Pointer (SP) – R13 1 Link Register (LR) – R14 holds the caller’s return address 1 Program Counter (PC) – R15 1 Current Program Status Register (CPSR)

  6. ARM Registers • ARM processors, with the exception of ARMv6-M and ARMv7-M based processors, have a total of 37 or 40 registers depending on whether the Security Extensions are implemented. • registers are arranged in partially overlapping banks. • There is a different register bank for each processor mode. • The banked registers give rapid context switching for dealing with processor exceptions and privileged operations. • Additional registers are available in privileged software execution.

  7. ARM Registers Additional registers in ARM processors, with the exception of ARMv6-M and ARMv7-M, are: 2 supervisor mode registers for banked SP and LR 2 abort mode registers for banked SP and LR 2 undefined mode registers for banked SP and LR 2 interrupt mode registers for banked SP and LR 7 FIQ mode registers for banked R8-R12, SP and LR 2 monitor mode registers for banked SP and LR 6 Saved Program Status Register (SPSRs), one for each exception mode.

  8. Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers Current Visible Registers r0 r0 r0 r0 r0 r0 r0 Abort Mode SVC Mode Undef Mode FIQ Mode User Mode IRQ Mode r1 r1 r1 r1 r1 r1 r1 r2 r2 r2 r2 r2 r2 r2 Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers Banked out Registers r3 r3 r3 r3 r3 r3 r3 r4 r4 r4 r4 r4 r4 r4 r5 r5 r5 r5 r5 r5 r5 User User User User User FIQ FIQ FIQ FIQ FIQ FIQ IRQ IRQ IRQ IRQ IRQ IRQ SVC SVC SVC SVC SVC SVC Undef Undef Undef Undef Undef Undef Abort Abort Abort Abort Abort Abort r6 r6 r6 r6 r6 r6 r6 r7 r7 r7 r7 r7 r7 r7 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r8 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r9 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r10 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r11 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r12 r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) r15 (pc) cpsr cpsr cpsr cpsr cpsr cpsr cpsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr spsr The ARM Register Set

  9. Processor Status Register(PSR) Contains: Condition flags that are set  by arithmetic and logical CPU instructions and used for conditional execution Greater than or equal to Mode bits Data Endianness bit Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than

  10. Processor Status Register(PSR) • The N, Z, C, and V bits are the condition code flags. • Flags are set  by arithmetic and logical CPU instructions and used for conditional execution • The processor tests these flags to determine whether to execute a conditional instruction. N – negative / less than Z – zero C – carry / borrow / extend V – overflow

  11. Processor Status Register(PSR) • Q sticky overflow. set to 1 when saturation occurs during QADD, QDADD, QSUB or QDSUB, or the result of SMLAxy or SMLAWx overflows 32-bits The Q flag is sticky in that, when an instruction sets it, this bit remains set until an MSR instruction writing to the CPSR explicitly clears it. Instructions cannot execute conditionally on the status of the Q flag.

  12. Processor Status Register(PSR) Also Contains: • Interrupt enable/disable flags for standard (IRQ) and fast (FIQ) interrupts. • Thumb bit set on Thumb Instruction execution. • Mode bits that indicate the current operating mode. • The PSR can be accessed by the MSR or LDM instructions. • Each operation mode has a shadow register for the current state of the PSR. The shadow registers are called SPSR (saved processor status register) whereas the CPSR holds the current state.

  13. ARM Comments • Another way to make your code more readable is to use comments! • The at symbol, @, is used for ARM comments in QEMU • anything from @ to end of line is a comment and will be ignored • /* comment */, is also available

  14. Immediates • Immediates are numerical constants. • They appear often in code, so there are ways to indicate their existence • Add Immediate: /* f = g + 10 (in C) */ ADD r0, r1, #10 @ (in ARM) where ARM registers r0, r1 are associated with C variables f, g • The second operand is a #number instead of a register.

  15. ARM Instructions • Instruction syntax: opcode{cond}{flags} Rd, Rn, operand2 where: • {cond} is an optional two-letter condition, e.g. EQ • {flags} is an optional additional flag, e.g. S • Rd is the destination register • Rn is the first source register • Operrand2 is a flexible second operand • Syntax is rigid (for the most part): • 1 operator, 3 operands • Why? Keep Hardware simple via regularity

  16. ARM Instructions Note: • Operand2 is a flexible second operand to most instructions • it is passed through the barrel shifter (a functional unit that can rotate and shift values) • it can take one of three forms: • Immediate value: an 8-bit number rotated right by an even number of places • Register shifted by a value: a 5-bit unsigned integer shift. • Register shifted by a register: the bottom 8 bits of a register.

  17. ARM Instructions Examples of Operand2 • Immediate values • add r0, r1, #3 • mov r0, #15 • mov r1, #0x12 • Register shifted by a value • mov r0, r1, lsl #4 • orr r1, r1, lsr #10 • Register shifted by a register • cmp r1, r2, lsl r0 • add r5, r3, ror r0

  18. Move instructions • mov Rd Operand2 • mvn Rd 0xFFFFFFFF EOR Operand2 • Examples mov r0, #15 mov r0, r1

  19. Compare instructions • cmp – compare • Flags set to result of (Rn – Operand2) • cmn – compare negative • Flags set to result of (Rn + Operand2) • tst – bitwise test • Rd := Rn or Operand2 • teq – test for equivalence • Rd := Rn and not Operand2

  20. Compare instructions • Comparisons produce no results – they just set condition codes. • Ordinary instructions will also set condition codes if the “S” bit is set. The “S” bit is implied for comparison instructions. • Examples of compare instructions cmp r0, r1 cmp r0, #10 tst r1, #1 teq r0, 41

  21. Logical instructions – Chapter 7 (pp 97 – 98) • and – logical and Rd Rn and Operand2 • eor– exclusive or Rd Rn eor Operand2 • orr – logical or Rd Rn or Operand2 • bic – bitwise clear Rd Rn and not Operand2 • Examples and r2, r0, r1 @ r2 = r0 & r1 eor r2, r2, #1 @ r2 = r0 ^ 1

  22. Arithmetic instructions (p. 104) • add Rd Rn + Operand2 • adc Rd Rn + Operand + Carry • sub Rd Rn – Operand2 • sbc Rd Rn – Operand2 – not(Carry) • rsb Rd Operand2 – Rn • rsc Rd Operand2 – Rn – not(Carry) • Examples add r2, r0, r1 @ r2 = r0 + r1 sub r2, r0, r1 @ r2 = r0 – r1

More Related