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Multicycle Control Step (1): Fetch

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Multicycle Control Step (1): Fetch. IR = Memory[PC]; PC = PC + 4;. 1. 1. 0. 0. 0. X. 010. 0. X. 1. 0. 1. Multicycle Control Step (2): Instruction Decode & Register Fetch. A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt])

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Multicycle Control Step (1): Fetch

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  1. Multicycle Control Step (1):Fetch IR = Memory[PC]; PC = PC + 4; 1 1 0 0 0 X 010 0 X 1 0 1

  2. Multicycle Control Step (2):Instruction Decode & Register Fetch A = Reg[IR[25-21]]; (A = Reg[rs]) B = Reg[IR[20-15]]; (B = Reg[rt]) ALUOut = (PC + sign-extend(IR[15-0]) << 2); 0 0 X 0 0 X 010 X X 0 0 3

  3. Multicycle Control Step (3):ALU Instruction (R-Type) ALUOut = A op B; 0 0 X 1 0 X ??? X X 0 0 0

  4. 2 0 1 M MUX 1 U X 0 0 M 0 M U U 1 X 1 0 X M U 1 X 0 1 M U 2 X 3 E X T N D Multicycle Control Step (4):ALU Instruction (R-Type) Reg[IR[15:11]] = ALUOut; (Reg[Rd] = ALUOut) 0 IRWrite I 28 32 0 I Instruction jmpaddr R <<2 CONCAT I[25:0] 5 PCWr* rs rt rd X X RegDst 0 32 5 5 1 XXX IorD ALUSrcA 5 PC Operation RN1 RN2 WN 3 MemWrite M ADDR PCSource Registers Zero D A X RD1 Memory ALU WD R RD ALU OUT B WD RD2 4 MemRead MemtoReg 1 RegWrite 0 1 ALUSrcB 16 32 immediate X <<2

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