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ISSUES IN TIMING

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This article explores the concept of clock skew in digital circuits, detailing its implications on edge-triggered logic and the performance of timing-critical designs. We examine the delay of clock wire, constraints associated with positive and negative skew, and explore how to counteract clock skew through effective clock distribution techniques. Additionally, we provide insights into the clock network with distributed buffering, using the DEC Alpha 21164 processor as a practical example of clock skew management in a master-slave two-phase design.

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ISSUES IN TIMING

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Presentation Transcript

  1. ISSUES IN TIMING

  2. The Clock Skew Problem

  3. Delay of Clock Wire

  4. Constraints on Skew

  5. Clock Constraints in Edge-Triggered Logic

  6. Positive and Negative Skew

  7. Clock Skew in Master-Slave Two Phase Design

  8. Clock Skew in 2-phase design

  9. How to counter Clock Skew?

  10. Clock Distribution

  11. Clock Network with Distributed Buffering

  12. Example: DEC Alpha 21164

  13. Clock Skew in Alpha Processor

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