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DCS – Frontend Monitoring and Control

DCS – Frontend Monitoring and Control. How does DCS see the FEE ?. Supervisory Layer. Well defined interface (OPC, DIM..). Private Software. DCS receives user requirements: which channels have to be controlled/monitored update frequency limits relations between subsystems (e.g HV-LV)

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DCS – Frontend Monitoring and Control

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  1. DCS – Frontend Monitoring and Control Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  2. How does DCS see the FEE ? Supervisory Layer Well defined interface (OPC, DIM..) Private Software • DCS receives user requirements: • which channels have to be controlled/monitored • update frequency • limits • relations between subsystems (e.g HV-LV) • interlock requirements • list of actions expected from DCS FEE DETECTOR Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  3. What is the other approach? DCS FEE DETECTOR Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  4. FEE Architectures in Alice DCS Supervisory Layer DCS “private” architecture Standard Software Interface Detector-DCS “Shared” architecture HARDWARE INTERFACE PRIVATE LINK FIELDBUS ETHERNET… FIELDBUS ETHERNET… Detector “private” architecture PRIVATE LINK A/D Conversion (e.g. PLC…) Control (setup of DCS Parameters…) Monitoring (Temp, I, V, Status…) DETECTOR Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  5. Example: SDD FEE Design Both Control and Monitoring based on Private Interfaces LV LV end-ladder card Interface to DCS FEE hybrid HV end-ladder card HV Interface to DCS LV SPD (2 drift volumes) 64 channels DCS chip Voltage Regulators PASCAL 64 AMBRA Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  6. Example: SSD FEE Design Both Control and Monitoring based on Private Interfaces Hybrid supply card ENDCAP Module Carrying ALABUF+ALCAPONE chips Voltage Regulators LV (8) FEROM Crates (12) A128C SSD JTAG control and setup of ALCAPONE JTAG monitoring of A128C (2) JTAG Distributors HV Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  7. Example: TRD FEE Design Both Control and Monitoring based on TCP/IP Ethernet Connection Control Workstation DCS Ethernet (TCPIP) Voltage Regulators Readout chamber MCM ADCs (Temp, I,V) DCS ADC (Humidity, I,V) MCM Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  8. Example: HMPID FEE Design Monitoring based on Fieldbus DCS (OPC) PLC MCM 1 Temperature Sensors ADC 1a (6) FEE Segments ADC 1b MCM 2 (6) HV Segments Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  9. Example: FEE in TPC Both Control and Monitoring based on Fieldbus Readout Chamber RCU DCS Network FEC Profibus (Ethernet…) Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  10. Example: SPD FEE Design SPD Alice 1 Pilot MCM Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  11. Example: SPD FEE Design SPD Alice 1 Pixel Chip Analog Pilot Pilot MCM Data + JTAG Out Digital Pilot GOL Clock Laser and pin diodes JTAG (in) Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  12. Example: SPD FEE Design Voltage Regulators Half Stave Power Supplies Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  13. Example: SDD FEE Design Voltage Regulators ~ 200 m R OUTER TTC (Trigger Timing and Control) DDL (Digital Data Link) DCS and Monitoring Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  14. Example: SPD FEE Monitoring Router PVSS VR Control, VR Status, I,V J T A G VR control DIM Halfstave control Memory Dedicated CPU (Workstation) DCS Data DDL Monitoring (Temp) DAQ Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  15. Present Configuration Model FEE DDL DAQ CONFIG DB Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  16. SPD FEE Configuration (DDL Approach) Router J T A G VR control Halfstave control Data DDL DAQ CONFIG DB Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  17. SPD Configuration Traps: Case1 – Faulty Chip Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  18. SPD Configuration Traps: Case1 – Faulty Chip X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  19. SPD Configuration Traps: Case1 – Faulty Chip X X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  20. SPD Configuration Traps: Case1 – Faulty Chip The Instruction length has been altered! The Data and its Size have been changed ! X X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  21. SPD Configuration Traps: Case1 – Faulty Register Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  22. SPD Configuration Traps: Case1 – Faulty Register X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  23. SPD Configuration Traps: Case1 – Faulty Register X X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  24. SPD Configuration Traps: Case1 – Faulty Register X X X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  25. SPD Configuration Traps: Case1 – Faulty Register X X X X Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  26. SPD Configuration Traps: Case1 – Faulty Register X X X X An completely altered set of instruction has been used! Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  27. SPD Operation Mode Analog Pilot Digital Pilot GOL Pixel Chip Laser and pin diodes JTAG (in) Data + JTAG Out JTAG IS INVOLVED IN ADC Monitoring Pixel chips are not accessible Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  28. SPD Configuration Mode Analog Pilot Digital Pilot GOL Pixel Chip Laser and pin diodes JTAG (in) JTAG IS INVOLVED IN CHIP CONFIGURATION ADCs on Analog Pilot are not accessible via DCS Data + JTAG Out Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  29. DAQ-DCS Synchronization with DDL involved Control CPU recognizes the request Control CPU informs the DCS DAQ initiates FEE setup (by sending a command) DCS releases the equipment and confirms the request Acknowledge DAQ starts polling the status Not Ready FEE Configuration Not Ready FEE Ready Ready Control CPU informs the DCS DCS + FEE DAQ Local Control DDL Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  30. Why do we need involve ECS in configuration? • It should be possible to reconfigure FEE without the presence of DAQ (recovery from power cut) • DCS may need to ask for reconfiguration in some cases (e.g. voltage regulator failure) Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  31. DAQ-DCS Synchronization with DDL involved ECS DAQ DCS ECS routes the request to DAQ DCS asks for reconfiguration of FEE FEE Configuration Ready DCS + FEE DAQ Local Control DDL Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  32. DAQ-DCS Synchronization with DDL involved ECS DAQ DCS ECS routes the request to local control CPU DCS asks for reconfiguration of FEE FEE Configuration Ready DCS + FEE DAQ Local Control DDL Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  33. DAQ-DCS Synchronization with ECS involved Router DCS - PVSS VR Control, VR Status, I,V J T A G VR control DIM Halfstave control Memory Dedicated CPU (Workstation) DAQ+DCS Data DDL ECS CONFIG DB DAQ Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  34. Standard Interfaces • Detectors responsibility is to provide an OPC server or DIM Server + Client along with the operation specifications • In this way the choice of hardware implementation is transparent to DCS • Any hardware modification will be reflected in corresponding software update Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  35. Service based protocol Client can subscribe to service and define the update policy Easy to implement on different platforms Based on COM Groups and Items represent hardware Each client should be able to access any OPC server Tied to Windows platform Standard Interfaces – What does it mean? DIM –custom protocol OPC – Industrial standard Name Server OPC Server The Real System Service Info Register services Request Service OPC Group HW0 HW1 OPC Item Commands OPC Item HW2 Server Client Subscribe to service OPC Item Service Data Source: C.Gaspar Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  36. Example: A VME based DCS System Local CPU MXI Physical Connection DCS Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  37. Example: A VME based DCS System Local CPU MXI Physical Connection DIM Server Logical Connection DIM Client DCS Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  38. Example: A VME based DCS System Embedded CPU Physical Connection DCS Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  39. Example: A VME based DCS System Embedded CPU Physical Connection DIM Server Logical Connection DIM Client DCS Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

  40. Example: A VME based DCS System Embedded CPU Physical Connection The underlying physical architecture is transparent for DCS Any modifications will appear at the level of the DIM server (the client may remain the same!) DIM Server Logical Connection DIM Client DCS Peter Chochula CERN-ALICE ALICE DCS Workshop, CERN September 16, 2002

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