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THE DESIGN OF THE MEMORY BUILT-IN SELF-TEST, DIAGNOSIS AND REPAIR (MBISTDR) FOR SRAMs. By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor DR BAMBANG SUNARYO SUPARJO
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THE DESIGN OF THE MEMORY BUILT-IN SELF-TEST, DIAGNOSIS AND REPAIR (MBISTDR) FOR SRAMs By WAN ZUHA WAN HASAN (UPM) DEPARTMENT OF ELECTRICAL, ELECTRONIC AND SYSTEM, FACULTY OF ENGINEERING UKM Supervised by PROF DR MASURI OTHMAN (UKM) Co-supervisor DR BAMBANG SUNARYO SUPARJO (MENTOR GRAPHIC USA)
Outline • Introduction • Memory Architecture • Memory Fault Models • Test Algorithms • Memory Testing, Diagnosis and Repair • Conclusion
Introduction Why BIST, BISD and BISR The advances of semiconductor memory technologies have become more complex and also the numbers of memory cell per chip (transistors) rapidly increase. The ITRS 2003 has shown an ever Increasing percentage of chip area devoted to embedded memory, with today’s SoCs already consisting of over 50% memory.
Introduction Memory Sizes Versus Yield
Introduction ITRS 2004 - SOC Test Requirements
Introduction The Requirement of Future MBISTDR • Fault Modeling – New Fault Models (defect in deep-submicron) • Test algorithm design – Optimal test/diagnosis (high defect coverage) • BIST – allow at speed testing • BISR – low cost repair scheme • ( improve the yield and reliability)
Memory architecture Functional RAM Model Source: Testing and semiconductor memories, A.J. van de Goor
Memory architecture Reduced Functional RAM Model Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models Source: Testing and semiconductor memories, A.J. van de Goor
Memory Fault Models Coupling Fault(CF)
Memory Fault Models Two Cell Faults - cont
State Coupling Fault Memory Fault Models Coupling Fault Source: Testing and semiconductor memories, A.J. van de Goor
Test AlgorithmsFunctional RAM Testing • Traditional Test - Zero-One - SAF - Checkerboard - SAF - GALPAT and Walking 1/0 – AF, SAF, TF and CF - testing time unacceptable - Sliding Diagonal – SAF, TF - Butterfly – SAF, AF Source: Testing and semiconductor memories, A.J. van de Goor
Test AlgorithmsMarch Test Notation Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms March Test Notation Source: Testing and semiconductor memories, A.J. van de Goor
Test Algorithms Source: Testing and semiconductor memories, A.J. van de Goor
March Test Algorithm Number Operation Fault Coverage Test-US MATS 4n or * 2N SAF, some AF MATS+ 2 5n or 5 * 2N SAF, AF Test-UT MATS++ 7 or 7 * 2N SAF, TF, AF Test-UC March C 11n SAF, TF, AF, CF Test-LC March A 15n SAF, AF, CF Test-LCT March B 17n SAF, AF, CF, TF Test Algorithms Comparison of March Tests Source: Testing and semiconductor memories, A.J. van de Goor
Test AlgorithmsFault detection using March C- M0 M1 M2 M3 {⇕(w0); (r0, w1); (r1, w0); (r0,w1); M4 M5 (r1, w0); ⇕(r0} - 10N Test algorithm Disable RAM (wait) { (r0, w1,); Disable RAM(wait) (r1):} - Data retention fault(DRF)
Test AlgorithmsFault detection using Extended March C- (covered SOF) M0 M1 M2 M3 {⇕(w0); (r0, w1,r1); (r1, w0); (r0,w1); M4 M5 (r1, w0); ⇕(r0)} - 11N Test algorithm Disable RAM (wait) { (r0, w1,); Disable RAM(wait) (r1):} - Data retention fault(DRF)
Test AlgorithmsFunctional Fault Models for Diagnosis ICCAD 2000 Chi-Feng Wu
Test AlgorithmsFault detection and diagnosis using March CL {(w0); (r0, w1,); (r1, w0,); ⇕(r1); R0 R1 R2 (r0,w1); ⇕(r1); (r1, w0); ⇕(r0)} R3 R4 R5 R6 -12N Test algorithm Disable RAM (wait){ (r0, w1,); Disable RAM(wait) (r1):} - Data retention Fault(DRF).
Test AlgorithmsFault detection and diagnosis by Extended March CL {(w0); (r0, w1, r1); (r1, w0); ⇕(r1); R0 R1 R2 R3 (r0,w1); ⇕(r1); (r1, w0); ⇕(r0)} R4 R5 R6 R7 -13N Test algorithm Disable RAM (wait){ (r0, w1,); Disable RAM(wait) (r1):}- Data retention Fault(DRF).
Test Algorithms Existing March Test Algorithms 1. { (w0); (r0, w1,); (r1, w0); (r0,w1); (r1, w0) }- Disable RAM (wait){(r0,w1,); Disable RAM(wait) (r1):} 9N test algorithm with data retention test – Rob Dekker 1988, has covered 100% coverage of the faults under the listed fault models. 2. { (w0); (r0, w1, r1, w0); delay (r0, r0); (w1); (r1, w0, r0, w1); delay (r1, r1)} 14N test algorithm - Said Hamdioui 2000, has covered 100% coverage of the faults under the listed fault models and spot defects.
Test AlgorithmsExisting March Test Algorithms 3. { (w0); (r0); delay (r0); (w1); (r1); delay (r1)} or { (w0); (r0); delay (r0); (w1); (r1); delay (r1)} 6N test algorithm – Baosheng Wang 2003, has reduced less than half of the required time for the 9N test algorithm 4. { ⇕(w0); (r0, w1,); ⇕(r1); (r1, w0); ⇕(r0); (r0, w1); ⇕(r1); (r1, w0); ⇕(r0); 13N test algorithm – V. N. Yarmolik 1996, has introduced diagnosis capability and achieved 63.6% diagnostic resolution (SAF & CF).
Test AlgorithmsExisting March Test Algorithms 5. { ⇕(w0); (r0, w1,r1, w0); (r0, w1); (r1, w0,r0, w1); ⇕(r1); (r1, w0); ⇕(r0); (r0, w1); ⇕(r1); 18N test algorithm – V. N. Yarmolik 1996, has been introduced for the diagnosis capability and achieved 90.9%diagnostic resolution (SAF & CF). 6. { (w0); (r0, w1, w0, w1); (r1, w0, r0, w1); (r1, w0, w1, w0); (r0, w1, r1, w0); Hold (r0, w1); Hold (r1); 20N test algorithm – I. Kim 1998, has been diagnosis capability and achieved 59% diagnostic resolution (SAF & CF).
Test AlgorithmsExisting March Test Algorithms 7. { (w0); (r0, w1,r1, w0 ); ⇕(r0); ⇕(w1); (r1, w0,r0, w1); ⇕(r1); } 12N test algorithm – T. J. Bergfeld 2000, has proposed diagnosis capability but it could only achieve 22.7% diagnostic resolution (SAF & CF). 8. { ⇕(w0); (r0, w1, r1); ⇕(r1); (r1, w0,r0); ⇕(r0); (r0, w1, r1); ⇕(r1); (r1, w0, r0); ⇕(r0); } 17N test algorithm – Jin-Fu Li 1996, has introduced diagnosis capability and achieved 100% diagnostic resolution(SAF & CF).
Test AlgorithmsExisting March Test Algorithms 9. {(w0); (r0, w1,); ⇕(r1); (r1, w0); (r0, w1); ⇕(r1); (r1, w0); ⇕(r0);} 12N test algorithm plus 3N or 4N ( for aggressor locating) – V. A. Vardanian 2002, has introduced diagnosis capability and achieved 100% diagnostic resolution.
Test Algorithms • STATE-OF-ART FOR TEST ALGORITHMS • Optimality in term of time complexity • Regularity and symmetry such that the self-test circuit can minimize the silicon area • High defect coverage and diagnosis capability in order to increase the repair capabilities and the overall yield
BIST CONTROLLER MBIST SYSTEM FSM COMPARATOR SRAM Memory Testing, Diagnosis and RepairMBIST ARCHITECTURE
BIST CONTROLLER MBISTD SYSTEM FSM COMPARATOR INDICATOR SRAM Memory Testing, Diagnosis and RepairMBISTD ARCHITECTURE
Memory Testing, Diagnosis and RepairBISTD • STATE-OF-ART FOR BISTD • Minimizing BIST overhead in both silicon area and routing • Supporting diagnosis capabilities • Supporting different kinds of memories (single-port, multi-port)
BIST CONTROLLER MBISTDR SYSTEM FSM COMPARATOR INDICATOR SRAM EXTRA COLUMN /ROW/WORD Memory Testing, Diagnosis and RepairMBISTDR ARCHITECTURE
Conclusion MBISTDR is essential for memory reliability in the near future. The addition of BISD and BISR will enhance the yields of overall memory chips. New test algorithm and fault syndromes base on March CL has been proposed to detect and diagnose SOF and AF.
THANK YOU Q & A
THANK YOU Q & A
