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FPGAs

FPGAs. Historically, FPGA architectures and companies began around the same time as CPLDs FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLD’s switch matrix.

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FPGAs

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  1. FPGAs • Historically, FPGA architectures and companies began around the same time as CPLDs • FPGAs are closer to “programmable ASICs” -- large emphasis on interconnection routing • Timing is difficult to predict -- multiple hops vs. the fixed delay of a CPLD’s switch matrix. • But more “scalable” to large sizes. • FPGA programmable logic blocks have only a few inputs and 1 or 2 flip-flops, but there are a lot more of them compared to the number of macrocells in a CPLD.

  2. General FPGA chip architecture a.k.a. CLB --“configurable logicblock”

  3. Xilinx 4000-series FPGAs

  4. FPGA specsmanship • Two flip-flops per CLB, plus two per I/O cell. • 25 “gates” per CLB if used for logic. • 32 bits of RAM per CLB if not used for logic. • All of this is valid only if your design has a “perfect fit”.

  5. Configurable Logic Block (CLB)

  6. CLB function generators (F, G, H) • Use RAM to store a truth table • F, G: 4 inputs, 16 bits of RAM each • H: 3 inputs, 8 bits of RAM • RAM is loaded from an external PROM at system initialization. • Broad capability using F, G, and H: • Any 2 funcs of 4 vars, plus a func of 3 vars • Any func of 5 vars • Any func of 4 vars, plus some funcs of 6 vars • Some funcs of 9 vars, including parity and 4-bit cascadable equality checking

  7. CLB input and output connections -- buried in the sea of interconnect

  8. Detail connectionscontrolled byRAM bits

  9. programmable switch element turning the corner, etc. Programmable Switch Matrix

  10. The fitter’s job • Partition logic functions into CLBs • Arrange the CLBs • Interconnect the CLBs • Minimize the number of CLBs used • Minimize the size and delay of interconnect used • Work with constraints • “Locked” I/O pins • Critical-path delays • Setup and hold times of storage elements

  11. Oh, by the way -- I/O blocks

  12. Problems common to CPLDs and FPGAs • Pin locking • Small changes, and certainly large ones, can cause the fitter to pick a different allocation of I/O blocks and pinout. • Locking too early may make the resulting circuit slower or not fit at all. • Running out of resources • Design may “blow up” if it doesn’t all fit on a single device. • On-chip interconnect resources are much richer than off-chip; e.g., barrel-shifter example. • Larger devices are exponentially more expensive.

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