1. Starting Materials Sub Sub TWG Teams

2. Yield - Defect Density Model Defect density increases as active area decreases for constant yield YieldDRAM = exp [- Di RiAeff] = 99% YieldMPU* = exp [- Di Ri T Ka (CD)2 ] = 99% YieldMPU** = exp [- Di Ri T  (CD)2 ] = 99% * Applied to those cases where the MPU analogous cell fill factor is “K” larger than the DRAM “a” value. “K” taken as 10 at present. ** Applied to those MPU (SOI) cases where the total transistor area, unique to SOI rather than Aeff, may be more appropriate (see footnotes to Tables). * Peter Zeitzoff / Allan Alan / Neil Gayle / Huff

3. 2001 Model Calculation for Effective Active Area * • For given DRAM chip area, Achip, there is memory cell area and periphery circuitry area • For memory area, with pass transistor width/length = CD • Total memory cell transistor area (T= # transistors) isPeriphery circuitry occupying remaining chip area is • Multiplying periphery circuitry area by 0.6 to get total periphery transistor area, the total effective active chip area can be written as * Peter Zeitzoff / Walter Class / Troy Messina / Huff