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Proposed Milestones and Timeline for CTL Memory Pin Functions Development

This document outlines the proposed milestones and timeline for the CTL construct, detailing all memory pins affecting memory testing. The integration of test pin information includes essential data such as pin names, ranges, directions (input/output), logical port relationships, and various pin functions such as ReadEnable, WriteEnable, and ECC-related functions. The team led by Sirinvas, alongside members Karen and Nicco, aims to establish a comprehensive overview to enable seamless integration of memory test information by drafting a complete document by February 2007.

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Proposed Milestones and Timeline for CTL Memory Pin Functions Development

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  1. Memory CTL Sub Teams

  2. Proposed Milestones and Timeline

  3. Pin Level Functions • Members • Sirinvas (Leader), Karen, Nicco • Scope: • Define CTL construct to describe all memory pins that may affect memory test to enable seamless integration of Test • Pin Information • Pin Name • Pin Range [L..R] • Direction (Input, Output, InOut) • Logical Port relationship • Polarity (Active High/Low) • Pin Function Data, Address, BistClock, ReadEnable, WriteEnable, ReadWriteEnable, MasterClock, BistEnable, SlaveClock, ScanClock, GroupWriteEnable, GroupReadWriteEnable, (None), Open, OutputEnable, ScanTest, ByPassEnable, MemSelect, ShiftEnable, Active, CAS, RAS, Refresh, ECCDisable, PipelineEnable, [User defined], CAMComparandInput, CAMComparandMask, CAMCompareEnable, CAMMatchOutput, CAMMatch, CAMMultiHit, CAMMatchAddress; ECCEnable, ECCTestInput, ECCDataOutput, ECCOuputEnable, <Repair Related Functions>, <Timing Margin Related Functions>, <ECC Correction>, <ECC Error>, <Power Down Functions>, <CAM Reset>, <Scan Clock Enable>, <Sync bypass Clock>, <MRAMs pin functions>, <Flash Memory Pin Functions>, <External memory pins>, <NVM pins>, • Mile Stone: Draft Document by Feb 2007

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