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This lecture focuses on the ideal behavior of 2-terminal MOS capacitors and diodes, detailing the flat-band, accumulation, depletion, and inversion regions. Key topics include surface states, capacitance calculations for oxide and silicon, and the equivalent circuits for various operating conditions. The effects of oxide charge and surface charge on capacitance-voltage (C-V) characteristics, along with threshold voltage calculations for n-channel and p-channel MOSFETs, are discussed. Visual aids illustrate important concepts, making the lecture valuable to students and professionals in semiconductor device theory.
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EE 5340Semiconductor Device TheoryLecture 25 - Fall 2010 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc
Ideal 2-terminalMOS capacitor/diode conducting gate, area = LW Vgate -xox SiO2 0 y 0 L silicon substrate tsub Vsub x
Flat band with oxidecharge (approx. scale) Al SiO2 p-Si +<--Vox-->- q(Vox) Ec,Ox q(ffp-cox) Ex q(fm-cox) Eg,ox~8eV Ec EFm EFi EFp q(VFB) Ev VFB= VG-VB, when Si bands are flat Ev
Equivalent circuitfor accumulation • Accum depth analogous to the accum Debye length = LD,acc = [eVt/(qps)]1/2 • Accum cap, C’acc = eSi/LD,acc • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’acc
Equivalent circuitfor Flat-Band • Surface effect analogous to the extr Debye length = LD,extr = [eVt/(qNa)]1/2 • Debye cap, C’D,extr = eSi/LD,extr • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’D,extr
Equivalent circuitfor depletion • Depl depth given by the usual formula = xdepl = [2eSi(Vbb)/(qNa)]1/2 • Depl cap, C’depl = eSi/xdepl • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’depl
Equivalent circuitabove OSI • Depl depth given by the maximum depl = xd,max = [2eSi|2fp|/(qNa)]1/2 • Depl cap, C’d,min = eSi/xd,max • Oxide cap, C’Ox = eOx/xOx • Net C is the series comb C’Ox C’d,min
Differential chargesfor low and high freq high freq. From Fig 10.27*
Ideal low-freqC-V relationship Fig 10.25*
Comparison of lowand high freq C-V Fig 10.28*
Effect of Q’ss onthe C-V relationship Fig 10.29*
Approximation concept“Onset of Strong Inv” • OSI = Onset of Strong Inversion occurs when ns = Na = ppo and VG= VTh • Assume ns = 0 for VG< VTh • Assume xdepl = xd,max for VG = VTh and it doesn’t increase for VG > VTh • Cd,min = eSi/xd,max for VG > VTh • Assume ns > 0 for VG > VTh
Fig 10.9* qfp 2q|fp| xd,max MOS Bands at OSIp-substr = n-channel
Computing the D.R. W and Q at O.S.I. Ex Emax x
Fully biased n-MOScapacitor VG Channel if VG > VT VS VD EOx,x> 0 e- e- e- e- e- e- n+ n+ p-substrate Vsub=VB Depl Reg Acceptors y 0 L
MOS energy bands atSi surface for n-channel Fig 8.10**
Ex Emax x Computing the D.R. W and Q at O.S.I.
Q’d,max and xd,max forbiased MOS capacitor Fig 8.11** xd,max (mm)
n-channel VT forVC = VB = 0 Fig 10.20*
p-channel VT forVC = VB = 0 Fig 10.21*
n-channel enhancementMOSFET in ohmic region 0< VT< VG Channel VS = 0 0< VD< VDS,sat EOx,x> 0 e-e- e- e- e- n+ n+ Depl Reg p-substrate Acceptors VB < 0
Conductance ofinverted channel • Q’n = - C’Ox(VGC-VT) • n’s = C’Ox(VGC-VT)/q, (# inv elect/cm2) • The conductivity sn = (n’s/t) q mn • G = sn(Wt/L) = n’s q mn (W/L) = 1/R, so • I = V/R = dV/dR, dR = dL/(n’sqmnW)
I-V relation for n-MOS (ohmic reg) ohmic ID non-physical ID,sat saturated VDS VDS,sat
References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986