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DSP + FPGA Supervisory Communications Infrastructure

DSP + FPGA Supervisory Communications Infrastructure. (more or less) 10 Aug 2001 M. Haney, University of Illinois and others to be held blameless. Muon Preprocessor. Pixel Preprocessor. Segment Preprocessor. Segment Preprocessor. Detector. Front End Board (DCB). Others. 1 Highway.

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DSP + FPGA Supervisory Communications Infrastructure

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  1. DSP + FPGA Supervisory Communications Infrastructure (more or less) 10 Aug 2001 M. Haney, University of Illinois and others to be held blameless

  2. Muon Preprocessor Pixel Preprocessor Segment Preprocessor Segment Preprocessor Detector Front End Board (DCB) Others... 1 Highway MTSM L1Buf PTSMRegionalControlandMonitoring L1Buf (raw) L1Buf (cooked) Crossing Switch /c/spot Muon DSP Farm BTeV Run Control L1Buf (basis) L1Buf (basis) Pixel DSP Farm L1Buf (basis) L1Buf (details) Opinions GLSM L1Buf (basis) GL1 L1Buf (details) Accept/Reject Decisions Resource Mgr Requested/AssignedCrossing data L2/L3 m-haney@uiuc.edu 10aug01

  3. Pixel (Muon) Trigger Supervisor Monitor (P/M)TSM • Control Functions: • Initialization • sets the maximum bandwidth necessary • can not take all day... • Command Parsing and Distribution • to subordinates, from RunControl • Error Response • autonomous, “local” (regional) • not to be confused with higher-level driven Error Handling, which appear as “Commands” m-haney@uiuc.edu 10aug01

  4. (P/M)TSM (continued) • Monitor Functions • Error Message Collection and Reporting • organized, formatted, sent higher up • Hardware and Software Status • not unlike Error Messages... • Status and Data Histogramming • utilizes remaining (P/M)TSM system bandwidth m-haney@uiuc.edu 10aug01

  5. Close-up: FPGA EtherNet,for example Preprocessorfor example... BTeV Run Controland database(s), etc. MonitoringAwareness _TSMRegional Controland Monitoring FPGA _TSMLocal Controland Monitoring Local Config(Flash) ARCNet,for example FPGA ControlInfluence JTAG,programming and debug /c/spot run StandaloneOperationalCapability Regional copyof config data,and history Power, Cooling Monitoringand Control Fire Detect m-haney@uiuc.edu 10aug01

  6. Close-up: DSP EtherNet,for example DSP BTeV Run Controland database(s), etc. MonitoringAwareness _TSMRegional Controland Monitoring FPGA _TSMLocal Controland Monitoring Local Config(Flash) ARCNet,for example DMAin Host PortInterface DSP BSPout ControlInfluence JTAG,programming,debug, and monitoring run(spot); run; StandaloneOperationalCapability Regional copyof config data,and history Power, Cooling Monitoringand Control Fire Detect m-haney@uiuc.edu 10aug01

  7. Factoids • ARCNet • 2.5 Mbps, 255 nodes (max), 500 byte packets (max), broadcast capability, “easy” • TMS320C67x DSP • ~70 Kbyte internal RAM, ~1200 MIP • fixed/floating point • TMS320C64x DSP • ~1 Mbyte internal RAM, ~3x faster… • fixed point only m-haney@uiuc.edu 10aug01

  8. More Factoids • Host Port Interface (TI DSP only) • almost-direct access into the DSP • peek, poke • uses DMA (like) resources… • (concept not unique to TI) • DMA • crossing data in • Buffered Serial Port(s) • opinions out; dual, ~75Mbps (C6x) m-haney@uiuc.edu 10aug01

  9. Even More Factoids • DSP/BIOS and RTDX (TI DSP only) • DSP/BIOS real time kernel • based on SPOX • RTDX uses JTAG to provide”zero” overhead monitoring and control • profiling • timing • messaging • “It’s in there!” • two less wheels to reinvent... m-haney@uiuc.edu 10aug01

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