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Ready in 2013

Next Generation Systems. European X-Ray Free Electron Laser XFEL DESY Laboratory, Hamburg. Ready in 2013. X-RAY Pixel Detectors DAQ For XFEL. FPGA. ATCA 8U Image Builders. Detector Pixel Sensors. SFP+. 1. 10G Fibre. 30 m.

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Ready in 2013

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  1. Next Generation Systems European X-Ray Free Electron Laser XFEL DESY Laboratory, Hamburg Ready in 2013

  2. X-RAY Pixel Detectors DAQ For XFEL FPGA ATCA 8U Image Builders Detector Pixel Sensors SFP+ 1 10G Fibre 30 m • Up to 16M? tiled pixel detector at 30K frames/s -> 160 GBytes/sec • Starting with 1 M pixel prototypes -> 10 GBytes/sec • On Detector up to 256 x FPGA 40nm + 10G links • Off Detector DAQ next gen Advanced Telecoms ATCA crate 10 GBytes/sec x N cards 8

  3. Common Fast Timing/Controls Output Buffers Clock, Reset Record Reg Out DDR2/QDR2 Osc FPGA Virtex 5 <~ 125 mm 128 x ASICs Opto Module 10 Gb SFP+ SFP+ PHY Opto on FMC Mezzanine? DC-DC Input Muxes ASIC status Cfg EPROM Linears Slow Controls 1 GbE Front End Card FEE On Detector (16 cards per 1 MPixel Detector) Main Components and Interfaces <~ 200 mm 10 Gb Data To XFEL Train Builder Slow Controls LAN Drawing is Not to Scale JTAG Power Connector • Changed to 1 FEM per Super Module (128 ASICs). 16 FEMs in total. • Readout with 10 Gb Optical links.Memory to balance data flow from ASICs to Optical Links. • Fast Timing and Controls. Expect a common system to be defined.

  4. X-RAY Pixel Detectors DAQ For XFEL FPGA ATCA 8U Image Builders Detector Pixel Sensors SFP+ 1 10G Fibre 30 m • Up to 16M? tiled pixel detector at 30K frames/s -> 160 GBytes/sec • On Detector 256 x FPGA 40nm + 10G links • Off Detector DAQ next gen Advanced Telecoms ATCA crates • 2009 - 2013… Scientific requirements ? 10 GBytes/sec x N cards 8

  5. FPGA FPGA FPGA FPGA SDRAM SDRAM SDRAM SDRAM Zone 3 Zone 2 SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ SFP+ PHY PHY PHY PHY PHY PHY PHY PHY Zone 1 FPGA FPGA FPGA FPGA SDRAM SDRAM SDRAM SDRAM ½ MPix ATCA 8U Train Builder. Matched to 2D 8 x FEE outputs “Simplest” Train Builder Implementation. All FPGA / No Mezzanines. RTM Cross point 10 Gb Outputs To Processors 10 Gb Inputs From Detectors DC-DC Confign ~40% scaling

  6. 148 mm Image Builder for XFELDemonstrator Advanced Mezzanine Card KEEP OUT K E E P O U T FMC 2 x SFP+ 10 Gbps RAM C O N N E C T O R FPGA • AMC Form Factor. • Migrating to 8 FPGAs on 8U ATCA? • FPGA ~ 16 x 3-6 Gbps serial links • Analogue Cross Point for Image Building. 72x72 @ 3-6 Gbps • DDR2/3 ~ 2-4 GBytes • B/W 1-2 GBytes/sec In & Out • VITA57 FMC Mezzanine I/O • 2 x SFP+ opto TRx • 10 Gbps (XAUI or RXAUI PHY) • mTCAserial backplane X-point TX MGT RX RX MGT C O N N E C T O R FMC 2 x SFP+ 10 Gbps FPGA C O N N E C T O R MGT MGT TX RAM KEEP OUT KEEP OUT 180 mm

  7. Next Generation Board Issues • High speed diff pairs 3-6 Gbps. BGA pitch < 1 mm? • Reduce Fabrication Risk. Advanced PCB design and construction techniques. • Vias in pad, micro vias, Laser drill. Incremental build up layer PCB. • FPGA 60-40nm generation? • FPGA to Memory interface. SO-RDIMMs WASSO • Memory controllers Hard/Soft IP from FPGA vendors • 10 Gbps optical interfaces • 3-6 Gbps Serial Backplanes. • Power. Multiple POL. Analogue. • Decoupling caps. next gen FPGA packages. • Pb Free manufacture? • Tools Signal Integrity analysis, how to measure eye diagrams on board?

  8. AMC FPGA SDRAM Opto Module 10 Gb SFP+ SFP+ PHY FPGA DDR2/QDR2 Osc FPGA Virtex 5 SDRAM DC-DC Cfg EPROM Linears SFP+ SFP+ SFP+ SFP+ PHY PHY Slow Controls 1 GbE Train Builder Development Plan 1. Demonstrator AMC cardwith CrossPoint. Prototype system using MicroTCA crate. Optical Mezzanine on AMC? 2009-10 2. On Detector cards 2009-2010 3. 1 Mega Pixel detectors : Full ATCA board Prototypes. With RTMs 2011-12 4. 1 Mega Pixel detectors: Full ATCA board Production with RTMs. 2013 5. Multi MegaPixel detectors 2014+ ?

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