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Integer Multipliers

Integer Multipliers

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Integer Multipliers

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  1. Integer Multipliers

  2. Multipliers • A must have circuit in most DSP applications • A variety of multipliers exists that can be chosen based on their performance • Serial, Serial/Parallel,Shift and Add, Array, Booth, Wallace Tree,….

  3. r e e s n e r t e e s n e t RA converter 16x16 multiplier Converter r RC e e s n e t RB converter

  4. Multiplication Algorithm X= Xn-1 Xn-2 …………………X0 Multiplicand Y=Yn-1 Yn-2…………………….Y0 Multiplier Yn-1X0 Yn-2X0 Yn-3X0 …… Y1X0 Y0X0 Yn-1X1 Yn-2X1 Yn-3X1 …… Y1X1 Y0X1 Yn-1X2 Yn-2X2 Yn-3X2 …… Y1X2 Y0X2 … … … … …. …. …. …. …. Yn-1Xn-2 Yn-2X0 n-2 Yn-3X n-2 …… Y1Xn-2 Y0Xn-2 Yn-1Xn-1 Yn-2X0n-1 Yn-3Xn-1 …… Y1Xn-1 Y0Xn-1 ----------------------------------------------------------------------------------------------------------------------------------------- P2n-1 P2n-2 P2n-3 P2 P1 P0

  5. A7.B1 A6.B1 A5.B1 A4.B1 A3.B1 A2.B1 A1.B1 A0.B1 . A7.B6 A6.B6 A5.B6 A4.B6 A3.B6 A2.B6 A1.B6 A0.B6 A3.B7 A2.B7 A1.B7 A0.B7 A3.B7 A2.B7 A1.B7 A0.B7 P15 P14 P13 P12 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 The equation is : . 1.Multiplication Algorithms Implementation of multiplication of binary numbers boils down to how to do the the additions. Consider the two 8 bit numbers A and B to generate the 16 bit product P. First generate the 64 partial Products and then add them up. A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 A7.B0 A6.B0 A5.B0 A4.B0 A3.B0 A2.B0 A1.B0 A0.B0 A7.B2 A6.B2 A5.B2 A4.B2 A3.B2 A2.B2 A1.B2 A0.B2 A7.B3 A6.B3 A5.B3 A4.B3 A3.B3 A2.B3 A1.B3 A0.B3 A7.B4 A6.B4 A5.B4 A4.B4 A3.B4 A2.B4 A1.B4 A0.B4 A7.B5 A6.B5 A5.B5 A4.B5 A3.B5 A2.B5 A1.B5 A0.B5

  6. Storage R E G I N 1 REG OUT MU (16X16 Multiplier Unit) Control Unit Multiplier Design

  7. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Slide 1

  8. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Slide 2

  9. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Slide 3

  10. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Slide 4

  11. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Slide 5

  12. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Slide 6

  13. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 7

  14. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 8

  15. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 9

  16. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 10

  17. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 11

  18. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 12

  19. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 13

  20. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 14

  21. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 15

  22. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 16

  23. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 17

  24. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 18

  25. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 19

  26. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 20

  27. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 21

  28. X: x3x2x1x0Y:y 3y2y1y0 Input Sequence for G1: 00x3x2x1x00x3x2x1x0 0x3x2x1x0 0x3x2x1x0 00y 3y3y3y3 0y 2y2y2y2 0y 1y1y1y1 0y 0y0y0y0 Reset:010000100001000010000 Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 21

  29. Si: the ith bit of the final result Slide 1

  30. Si: the ith bit of the final result Ci: the only carry from column i Slide 2

  31. Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 3

  32. Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 4

  33. Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 5

  34. Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 6

  35. Si: the ith bit of the final result Ci: the only carry from column i Sij: the jth partial sum for column i Cij: the jth partial carry from column i Slide 7

  36. Si: the ith bit of the final result Ci: the only carry from column i Slide 8

  37. INPUT Ain (7 downto 0) REGA 0 MUX INPUT Bin (7 downto 0) 8 bit Adder REGB REGC Result (7 downto 0) Result (15 downto 8) CLOCK Shift Add Multiplier Design Implementation

  38. Synchronous Shift and Add Multipliercontroller • Multiplication process: • 5 states: Idle, Init, Test, Add, and Shift&Count. • Idle: Starts by receiving the Start signal; • Init: Multiplicand and multiplier are loaded into a load register and a shift register, respectively; • Test: The LSB in the shift register which contains the multiplier is tested to decide the next state;

  39. Synchronous Shift and Add Multiplier ControllerDesign • Add: If LSB is ‘1’, then next state is to add the new partial product to the accumulation result, and the state machine transits to shift&count state ; • Shift&Count: If LSB is ‘0’, then the two shift register shift their contains one bit right, and the counter counts up byone step. After that, the state machine transits back to test state; • When the counter reaches to N , a Stopsignal is asserted and the state machine goes to the idle state; • Idle: In the idle state, a Donesignal is asserted to indicate the end of multiplication.

  40. n-bit Multiplier: Q0=1: Multiplicand is added to register A; the result is stored in register A; registers C, A, Q are shifted to the right one bit Q0=0: Registers C, A, Q are shifted to the right one bit Slide 1

  41. Example: 4-bit Multiplier Initial Values Slide 2

  42. Example: 4-bit Multiplier First Cycle--Add Slide 3

  43. Example: 4-bit Multiplier First Cycle--Shift Slide 4

  44. Example: 4-bit Multiplier Second Cycle--Shift Slide 5

  45. Example: 4-bit Multiplier Third Cycle--Add Slide 6

  46. Example: 4-bit Multiplier Third Cycle--Shift Slide 7

  47. Example: 4-bit Multiplier Fourth Cycle--Add Slide 8

  48. Example: 4-bit Multiplier Fourth Cycle--Shift Slide 9

  49. 4*4 Synchronous Shift and Add Multiplier DesignLayout Design Floor plan of the 4*4 Synchronous Shift and Add Multiplier

  50. Comparison between Synchronous and Asynchronous Approaches .