High Performance Interconnect and Packaging

1. High Performance Interconnect and Packaging Chung-Kuan Cheng CSE Department UC San Diego ckcheng@ucsd.edu

2. Research Scope Scalable System: Power, Delay, Cost, Reliability • Interconnect-Driven Designs • Wire Planning: Non-Manhattan Interconnect • Networks: Topology, Physical Layout • Clock & Power: Shunts + Trees (3) • Interconnect Style: Surfliner (2) • Datapath: Shifters, Adders, Mul. Div. • Packaging: Pin Breakaway (1) • Simulation • Static Timing Analysis: Hierarchy, Incremental • SPICE: Whole System Analysis

3. 1. Pin Breakaway • Interfaces of Chip and Package, Package and Board. • Breakaway of Array of Pins • Patterns of Breakaway • Obj: Cost= # Breakaway Layers

4. 1. Pin Breakaway • Row by Row Escape: Escape interconnect row by row from outside toward inside.

5. 1. Pin Breakaway (Cont.) • Parallel Triangular Escape: This method divides the objects into groups and escape each group with a triangular outline.

6. 1. Pin Breakaway (Cont.) • Central Triangular Escape: Escape objects from the center of the outside row and expands the indent with a single triangular outline.

7. 1. Pin Breakaway (Cont.) • Two-Sided Escape: Escape objects from the inside as well as from the outside. The outline shrinks slowly and also follow zigzag shape.

8. 1. Pin Breakaway (Cont.) Row by Row Parallel Triangles Central Triangle Two-Sided The movement of area array contour

9. 1. Pin Breakaway: Design Rules • Parameters used: • the pad pitch = 150m • the pad diameter = 75m • the line width = 20m • the spacing = 20m

10. 1. Pin Breakaway: Results 40 x 40

11. 1. Pin Breakaway: Results 20 x 20

28. 2. Interconnect Style: Surfliner • Global Interconnect trend • Scalability

29. 2. Surfliner - Features • Speed of light • < 1/5 Delay of Traditional Wires • Low Power Consumption • < 1/5 Power Consumption • Robust against process variations • Short Latency • Insensitive to Feature Size • Differential Signaling • Shield for low swing signals

30. 2. Surfliner:Transmission Line Model Differential Lossy Transmission Line Surfliner Add shunt conductance G= RC/L • Flat response from DC to Giga Hz • Telegraph Cable: O. Heaviside in 1887. Shunt conductance G= 0 for wires of IC

31. 2. Surfliner: Distortionless Line • Telegrapher’s equation: • Propagation Constant: • Wave Propagation: • Alpha and Beta corresponds to speed and phase velocity.

32. 2. Surfliner: Distortionless Lines • Set G=RC/L • Attenuation and Beta • Characteristic impedance: (pure resistive) • Phase Velocity (Speed of light in the media) • Attenuation:

33. 2. Surfliner: Distortionless Lines

34. 2. Surfliner: Performance • Speed of Light: 5ps/mm or 50ps/cm • Power: 10mW at GHz • Conductance variation = 10%, f=10MHz~10GHz • Attenuation and velocity variation < 1%

35. 2. Surfliner: Implementation • Add shunt conductance • Resistors realized by serpentine unsilicided poly, diffusion resistors, or high resistive metal

36. 2. Surfliner: Simulation Results • Characteristic Impedance (at 10GHz) : 39.915 Ohm • Inductance: 0.22nH/mm Capacitance: 141fF/mm • Attenuation: 253mv magnitude at receiver’s end (assuming 1V at sender’s end) • Using Microstrip (free space above the wires): impedance can be improved to 52.8Ohm

37. 2. Surfliner: Settings • Agilent ADS Momentum extract 4-port S-parameters • HSpice: Transient analysis • Assume 1023 bit pseudo random bit sequence (PRBS) • 15GHz clock • 10% of clock period transition slope for each rising and falling edge

38. 2. Surfliner: Simulation Results 120 Stages 4 Stages

39. 2. Surfliner: Simulation Jitter and silicon area usage Power w/ different width and separation

40. 2. Applications of Surfliner 1.Clock distributions 2. Data communications: Buses Between CPUs, DSPs, Memory Banks

41. 2. Application of Surfliner 3. High Performance Low Power Wafer Packaging

42. 2. Surfliner: Current Status • What we have done • Derived a conservative design • Performed simulation • We are looking forward to • Design and fabricate the test chip • Explore architectures to exploit the advantages of Surfliner

43. 3. Clock Distribution: Shunts + Trees 3.1 RC Shunts 3.2 Inductive Effects Contribution: • Analytical skew expression • Formulation of Multilevel Optimization • Empirical Observation

44. 3. Clock: Linear Variations Model • Process variation model • Transistor length • Wire width • Linear variation model • Power variation model • Supply voltage varies randomly (10%)

45. 3.1 Clock: RC Model Input: an n level meshes and h-trees Constraint: routing area, parameter variations Objective: skew

46. Simplified Circuit Model

47. Transient Response when t<T VS1=u(t) Vs2=0 Let Then V1 = A + B V2 = A - B

48. Skew Expression • Assumptions: • T<<RsC • Rs /R <<RsC/T • Using first order • Taylor’s expansion

49. Spice Validation of Skew Function

50. Skew on mesh • Conjectured skew expression • Using regression to get k