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EE587 SoC Design & Test

EE587 SoC Design & Test

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EE587 SoC Design & Test

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  1. EE587SoC Design & Test Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 1

  2. Lecture 1Design and Technology TrendsOverview Lecture 1

  3. Recent Trends • 1.5GHz Itanium chip (Intel), 410M tx, 374mm2 , 130W@1.3V • 1.1 GHz POWER4 (IBM), 170M tx, 115W@1.5V • if these trends continue, power will become unmanageable • 150Mhz Sony Graphics Processor, 7.5M tx (logic) + 280M tx (memory) = 288M tx, 400mm2 10W@1.8V • if trend continues, most designs in the future will have a high percentage of memory • Single-chip Bluetooth transceiver (Alcatel), 400mm2, 150mW@2.5V • required 30 designers over 2.5 years (75 person-years) • if trend continues, it will be difficult to integrate larger systems on a single chip in a reasonable time Lecture 1

  4. Multi-Core Design • Intel’s 80-core chip • In 65-nm technology with 80 single-precision, floating point cores delivers performance in excess of a teraflops while consuming less than 100 w. • A 2D on-die mesh interconnection network operating at 5 GHz provides the high-performance communication fabric to connect the cores. • Interconnects are the biggest bottleneck • We need to look beyond the metal/dielectric-based planar architectures • Optical, 3D integration and Wireless are the emerging alternatives Lecture 1

  5. Multi-core applications Nokia Sparrow Intel LARRABEE Lecture 1

  6. Three-Dimensional Integrated Circuits As small as 20µm 2D IC 3D IC Lecture 1 • Coming in a big way • Multiple Layers of Active Devices • Driven by • Limited floorplanning choices • Desire to integrate disparate technologies (GaAs, SOI, SiGe, BiCMOS) • Desire to integrate disparate signals (analog, digital, RF) • Interconnect bottleneck 6

  7. Photonic Communication High bandwidth photonic links for high payload transfers Limitations on switch architecture More than 4-port designs are complex On-chip integration of photonic components Lecture 1

  8. On-Chip RF/Wireless Interconnects Replace long distance wires Use of waveguides out of package or IC structures like parallel metal wires Chang et al. demonstrated Transmission Line based RF interconnect for on chip communication Not really wireless Lecture 1

  9. Novel interconnect paradigms for Multicore designs Three Dimensional Integration Wireless/RF Interconnects Optical Interconnects Lower Latency and Energy Dissipation Lecture 1

  10. MOS Transistor Scaling(1974 to present) Scaling factor s=0.7 per node (0.5x per 2 nodes) Technology Node set by 1/2 pitch (interconnect) Metal pitch Poly width Gate length (transistor) Lecture 1

  11. Ideal Technology Scaling (constant field) Lecture 1

  12. Technology Nodes 1999-2019 1999 2001 2004 2007 2010 2013 2016 2019 0.7x 0.7x 180nm 130nm 90nm 65nm 45nm 32nm 22nm 16nm 0.5x N-1 N N+1 Two year cycle between nodes until 2001, then 3 year cycle begins. Lecture 1

  13. MPU Clock Frequency Trend Intel: Borkar/Parkhurst Lecture 1

  14. MPU Clock Frequency Trend 10000 Forward projection may be too optimistic P4 1000 100 80386 80486 Pentium Pentium II Expon. 10 Dec-83 Dec-86 Dec-89 Dec-92 Dec-95 Dec-98 Dec-99 Dec-00 Dec-01 Dec-02 Lecture 1 Intel: Borkar/Parkhurst

  15. MPU Clock Cycle Trend (FO4 Delays) Intel: Borkar/Parkhurst Lecture 1

  16. Optimal Sizing - FO4 Concept where g is ratio of Parasitic output Capacitance to gate capacitance Use FO4 delay as optimal delay 1X 4X 16X C Cload IN Lecture 1

  17. Clock cycle trend Lecture 1

  18. Transistors DoubleEvery Two Years 10,000 1,000 100 Transistors(MT) 10 P6 Pentium® proc 486 1 386 2X Growthin 2 Years! 0.1 286 8086 8085 0.01 8080 8008 4004 0.001 ’70 ’80 ’90 ’00 ’10 MPU Trends - Moore’s Law Source: Intel Lecture 1

  19. 100 41 36 32 28 Pentium® Pro proc Die size(mm) Pentium® proc 486 10 386 286 8080 8086 8085 8008 4004 ~7% growth per year ~2X growth in 10 years 1 ’70 ’80 ’90 ’00 ’10 More MPU Trends ~40mm Die in 2010? Source: Intel Lecture 1

  20. Sun’s Surface Rocket Nozzle Nuclear Reactor Hot Plate Power Projections Too High! 10,000 1,000 Pentium® processors Power(Watts) 100 286 486 8086 10 386 8085 8080 8008 1 4004 0.1 ’71 ’74 ’78 ’85 ’92 ’00 ’04 ’08 What about power in the future? Source: Intel Lecture 1

  21. Problem with Power and Speed • Power knob running out • Speed == Power • 10W/cm2 limit for convection cooling, 50W/cm2 limit for forced-air cooling • Large currents, large power surges on wakeup • Die size will not continue to increase unless more memory is used to occupy the additional area • additional power dissipation coming from subthreshold leakage • Speed knob running out • Historically, 2x clock frequency every process generation • 1.4x from device scaling • 1.4x from pipelining, hence fewer logic stages (from 40-100 down to around 16 FO4 INV delays) • Clocks cannot be generated with period < 6-8 FO4 INV delays • Around 14-16 FO4 INV delays is limit for clock period Unrealistic to continue 2x frequency trend! Lecture 1

  22. Low-Power Application: PDA 0.18um / 400MHz / 470mW (typical) MM Application MP3 JPEG SimpleMoving Picture CPG PWR Processor Area PWM RTC CPU FICP SSP 6.5MTrs. I2C I-cache 32KB GPIO D-cache 32KB Sound Max 400MHz USB USB OST DMA controller MMC MMC I2S Available Time 6-10Hr LCD Cnt. MEM Cnt. KEY UART AC97 Data Transfer Area LCD Flash 32MB SDRAM 64MB Peripheral Area 100MHz 4 – 48MHz Lecture 1

  23. Trends in Low-Power Design Content • Today, SoC designs contain embedded processing engines such as CPU and DSP, and memory blocks such as SRAM and embedded DRAM • As we scale technology and keep power constant how does the amount of logic vs. memory change? • Consider the following assumptions to develop trends for on-chip logic/memory percentages • Die size is 100mm2 • Clock frequency starts at 150MHz increases by about 40% per technology node • Average power dissipation in limited to 100mW at 100oC • Initial condition at Year 2001: area percentage 75% logic, 25% memory Lecture 1

  24. ASIC Logic/Memory Content Trends • Source: Dataquest (2001) Lecture 1

  25. Design Trend: Productivity Gap Lecture 1

  26. Designing a 50M Transistor IC • Gates Required ~12.5M • Gates/Day (Verified) 1K (including memory) • Total Eng. Days 12,500 • Total Eng. Years 35 • Cost/Eng./Year $200K • Total People Cost $7M • Other costs (masks, tools, etc.) $8M Actual Cost is $10-15M to get actual prototypes after fabrication. Lecture 1

  27. Productivity Gap • Deep submicron (DSM) technology allows hundreds of millions of transistors to be integrated on a single chip • Number of transistors that a designer can design per day (~1000 gates/day) is not going up significantly • New design methodologies are needed to address the integration/productivity issues  “System on a chip” Design with reusable IP (Intellectual Property) • new design methodology, IP development • new HW/SW design and verification issues • new test issues Lecture 1

  28. SoC Design Hierarchy SOC consists of new logic blocks and existing IP New Logic blocks Existing IP including memory Each logic block can be implemented by newly designed portion and a re-use portion based on IPs Newly designed portion Re-use portion including memory Lecture 1

  29. Foundation Block + Reference Design Pre-Qualified/Verified Foundation-IP* Scaleable bus, test, power, IO, clock, timing architectures MEM Hardware IP Processor(s), RTOS(es) and SW architecture CPU FPGA SW IP Programmable IP Foundry-Specific Pre-Qualification SoC Platform Design Concept Application Space Methodology / Flows: System-level performance evaluation environment HW/SW Co-synthesis SoC IC Design Flows *IP can be hardware (digital or analog) or software. IP can be hard, soft or ‘firm’ (HW), source or object (SW) SoC Verification Flow System-Level Performance Evaluation Rapid Prototype for End-Customer Evaluation SoC Derivative Design Methodologies Lecture 1

  30. Purpose of this Course • This course addresses SoC design & test in DSM technologies • The goal is to present an overview of the various issues from “Systems to Silicon” to provide a perspective on what is happening in technology and design. • It is a very broad subject, one that industry is grappling with on a daily basis – one course cannot address all the issue properly • We will begin with the Systems Level and work our way down to the Circuits Level • The projects, presentations, and assignments will provide in-depth analysis of the subjects that are of interest to you Lecture 1

  31. Syllabus • Three broad categories • System on chip design and design for testability • Role of interconnectsin contemporary SoC Design • Importance of Power and Low power SoC design methodology Lecture 1

  32. References • Analysis and Design of Digital Integrated Circuits - In Deep Submicron Technology, Hodges, Jackson and Saleh, McGraw-Hill, Third Edition, 2004 • Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits by M. L. Bushnell and V. D. Agrawal, Boston: Springer, 2005, ISBN 0-7923-7991-8 • Journal Papers, Conference Papers, Course Notes. Lecture 1

  33. Assignments • There will be several homework and reading assignments. In reading assignments students are expected to read research papers and submit summaries. The reading list will be available on the course website. In class, you will be told which papers you should review. • Each student will have the opportunity to present one paper to the class. The list of papers will be available in the course website. Each student should choose one of the listed papers. Lecture 1

  34. Project • One Design Project • List of possible projects will be provided • You are free to choose your own project. In that case Instructor’s approval is needed. Lecture 1