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ECE 2110: Introduction to Digital Systems

ECE 2110: Introduction to Digital Systems. Chapter 6 Review. Documentation Standards. Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system. Generally, documentation include:

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ECE 2110: Introduction to Digital Systems

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  1. ECE 2110: Introduction to Digital Systems Chapter 6 Review

  2. Documentation Standards • Documentation of a digital system should provide the necessary information for building, testing ,operating , and maintaining the system. • Generally, documentation include: 1) A Specification describes what the circuit is supposed to do. 2) A block diagram showing the inputs, outputs, the main building blocks ( modules) of the system and how they are connected. 3) A schematic diagram showing all the components, their types, and all interconnections. 4) A timing diagram showing the logic signals as a function of time. 5) A Circuit description explaining of the operation of the logic circuit.

  3. Block Diagram • A block diagram should show all inputs and outputs , the building blocks and their function names , and the data flow paths ( the logic signals).- The internal details of each block should not be shown.- Related logic signals are combined together and drawn with a double or heavy line, known as a bus • Example: Min/Max Circuit MIN/MAX X Comparator Y X>Y max(X,Y) Mux A bus is a collection of 2 or more related signal lines. Mux Z Mux min(X,Y)

  4. Schematic Diagram • Details of component inputs, outputs, and interconnections • Reference designators • Pin numbers • Gate symbols • Signal names and active levels • Bubble-to-Bubble Logic Design • Layouts

  5. DeMorgan equivalent symbols Which symbol to use? Answer depends on signal names and active levels.

  6. Active Levels • Each signal name should have an active-level associated with it. A signal is active-high if it performs the named action or denotes the named condition when it’s HIGH or 1. A signal is active-low if it performs the named action or denotes the named condition when it’s LOW or 0. • The signal is asserted when it is in its active level and negated ( or deasserted ) when its not in its active level. • Different naming conventions for active levels available.

  7. Bubble-to-Bubble Logic Design Rules • - The active level of the output signal of a logic device should match the active level of the device’s output pin.Active-low if the device symbol has an inversion bubble, active-high if not. - If the active level of an input signal is the same as that of the device’s input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is asserted.Most common case. - If the active level of an input signal is the opposite of that of the input pin to which it’s connected, then the logic function inside the symbolic outline is activated when the signal is negated. Should be avoided. ERROR ERROR OVERFLOW HALT_L READY READY_L ERROR REQUEST REQUEST FAIL_L ERROR ENABLE_L ENABLE OVERFLOW_L

  8. Timing Diagrams • A timing diagram illustrates the logical behavior of signals as a function of time. • Causality: which input transitions cause which output transitions. • Different through a circuit paths may have different delays. • A signal timing diagram may contain many different delay specifications. • Delay depends on - Internal circuit structure- Logic Family type- Source Voltage- Temperature

  9. Propagation Delay • The delay time between input transitions and the output transitions due to the propagation delay of the the logic gates. • tp of a signal depends on the signal path inside the logic circuit • For a logic gate tpLH may not equal tpHL • tp is specified in the manufacturer data sheets of the IC’s • Example : -The time delay for 74x00 in nanosecods for three Logic Families: • To find tp for a signal, add the propagation delays of all gates along the path of the signal

  10. Timing analysis • Study logical behavior of SSI/MSI devices • Delay info for some SSI and MSI devices (Tables 6-2, 6-3) • Worst-case delay: • Maximum of tpLH andtpHL for each component • Sum of the worst-case delays through the individual components, independent of the transition direction and other conditions.

  11. Combinational Building Blocks • 1-Decoders : Binary Decoders, Implementing Logic Functions • 2-Encoders : Binary Encoder, Encoder applications • 3- Multiplexers MUX operation, Single outputs MUX, Multiple output MUX, Implementing Logic Functions

  12. 4- Demultiplexers MUX/DMUX operation, Using Decoders as Demultiplexers. • 5- XOR Gates Logic Symbols, Equivalent Symbols, Parity circuits using XOR gate, • 6-Adders/Subtractors : Half Adder, Full Adder, Ripple Adder • 7- Arithmetic Logic Units

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