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Establishing a hub for R&D in digital systems with academic & industrial partners, focusing on SOC. Research areas include hierarchical test generation, fault simulation, test binding, and allocation. Developing new tools for system diagnostic modeling, test generation, and fault modeling in collaboration with partners in Estonia and abroad. Enhancing research environment to improve productivity and international cooperation. Impact on teaching with updated methodologies and content. Dissemination through conferences, tutorials, and courses.
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Facilitate the R&D in the field of design and testing of digital systems focused in SOC towards creating a Virtual Centre of Excellence for IST:
academic and industrial partners abroad (Germany, Sweden, Italy, Poland, Slovakia etc.)
implementing the results in Estonian industry (Artec Design, Liewenthal Electronics, National Semiconductors Estonia etc.)
hierarchical test generation and fault simulation for digital systems
The experimental research environment will be strengthened by developing new tools for system diagnostic modeling, test generation, fault modeling, simulation and diagnosis, design for testability, and built-in self-test. The enhancements in environment will contribute in
New teaching methodologies with updated content will be developed based on the new research results and new tools. The main concepts to be developed and implemented are
Tutorials in High-Level Design and Test – Tallinn, 2003, 2004, 2005