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Digital Design with VHDL

This detailed presentation on Digital Design with VHDL covers essential concepts and structures such as concurrent and sequential statements, signal assignments, component instantiation, and block statements. You'll learn how to implement D flip-flops with guard expressions and explore various architecture designs. The guide touches on configuration, including usage clauses and component specifications. This resource is invaluable for students and professionals aiming to master VHDL for digital circuit design. For inquiries, contact Amir Masoud Gharehbaghi at amgh@mehr.sharif.edu.

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Digital Design with VHDL

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  1. Digital Design with VHDL Presented by: Amir Masoud Gharehbaghi Email: amgh@mehr.sharif.edu

  2. Concurrent Statements • Concurrent Signal Assignment • Component Instantiation Statement • Generate Statement • Process Statement • Block Statement • Concurrent Procedure Call Statement • Concurrent Assert Statement

  3. Sequential Statements • Signal Assignment Statement • Variable Assignment Statement • IF Statement • Case Statement • Loop Statement • Wait Statement • Procedure Call Statement

  4. Sequential Statements (cont.) • Next Statement • Exit Statement • Return Statement • Assertion Statement • Report Statement • Null Statement

  5. Block Statement block_label: BLOCK [ (guard_expression) ] [ IS ] block_header block_declarative_part BEGIN block_statement_part END BLOCK [ block_label ] ;

  6. D-FF Example ARCHITECTURE guarding OF d_ff IS BEGIN dff_blk: BLOCK (c = ‘1’ AND NOT c’STABLE) BEGIN q <= GUARDED d; END BLOCK; END guarding;

  7. D-FF with block header ARCHITECTURE guarding_h OF d_ff IS BEGIN dff_blk: BLOCK (c = ‘1’ AND NOT c’STABLE) PORT(din: IN BIT; qout: OUT BIT); PORT MAP (din => d; qo => q); BEGIN qout <= GUARDED din; END BLOCK; END guarding_h;

  8. D-FF with enable ARCHITECTURE nested_guard OF d_ff_e IS BEGIN edge: BLOCK (c = ‘1’ AND NOT c’STABLE) BEGIN enable: BLOCK (e = ‘1’ AND GUARD) BEGIN q <= GUARDED d; END BLOCK; END BLOCK; END nested_guard;

  9. Resolution Function FUNCTION anding (drivers: IN BIT_VECTOR) RETURN BIT IS VARIABLE acc: BIT := ‘1’; BEGIN FOR I IN drivers’RANGE LOOP acc := acc AND drivers(i); END LOOP; RETURN acc; END anding; … SIGNAL a: anding BIT; … a <= b; a <= c; a <= d;

  10. Configuration CONFIGURATION identifier OF entity_name IS { use_clause } FOR architecture_name { block_configuration } END FOR ; END CONFIGURATION; block_configuration ::= FOR block_specification { use_clause } { configuration_item } END FOR ;

  11. Configuration (cont.) configuration_item ::= block_configuration | component_configuration component_configuration ::= FOR component_specification [ binding_indication ; ] [ block_configuration ] END FOR ;

  12. Configuration Example CONFIGURATION default_c OF test_comp4 IS FOR customizable FOR a1: comp4 USE ENTITY WORK.nc4(flexible); FOR c0, c3: comp1 USE ENTITY WORK.bc1(fixed);END FOR; FOR c2to3: comp1 USE ENTITY WORK.bc1(fixed); END FOR; FOR flexible END FOR; END FOR; END FOR;

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